High-performance Enhancement-mode GaN Power MIS-FET with Interface Protection Layer

Abstract

Effective interface protection techniques have been successfully developed to insert a sharp and thermally stable interlayer between the LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The interlayer plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at $\sim780 \circ C$) process, which is essential for fabricating enhancement-mode $LPCVD-SiN_{x}/GaN$ MIS-FETs with high stability and high reliability. With interface protection layer and reliable $LPCVD-SiN_{x}$ gate dielectric, the normally-off fully-recessed MIS-FET delivers remarkable advantages in high threshold voltage $(V_{th})$ thermal stability, long time-dependent gate dielectric breakdown (TDDB) lifetime and low bias temperature instability (BTI).