{"title":"An 11-bit 250MS/s subrange-SAR ADC in 40nm CMOS","authors":"Shushu Wei, X. Gu, Fule Li, Zhihua Wang","doi":"10.1109/ISNE.2016.7543365","DOIUrl":null,"url":null,"abstract":"This paper presents an 11-bit 250MS/s subrange SAR ADC. The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. The design is fabricated in a 40nm low-leakage process, and the core area is 0.018mm2. The post layout simulation achieves an ENOB of 9.99 bits at Nyquist input and consumes 1.5mW from 1.1V supply, leading to a FOM of 5.86fJ/conv-step.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an 11-bit 250MS/s subrange SAR ADC. The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. The design is fabricated in a 40nm low-leakage process, and the core area is 0.018mm2. The post layout simulation achieves an ENOB of 9.99 bits at Nyquist input and consumes 1.5mW from 1.1V supply, leading to a FOM of 5.86fJ/conv-step.