An 11-bit 250MS/s subrange-SAR ADC in 40nm CMOS

Shushu Wei, X. Gu, Fule Li, Zhihua Wang
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Abstract

This paper presents an 11-bit 250MS/s subrange SAR ADC. The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. The design is fabricated in a 40nm low-leakage process, and the core area is 0.018mm2. The post layout simulation achieves an ENOB of 9.99 bits at Nyquist input and consumes 1.5mW from 1.1V supply, leading to a FOM of 5.86fJ/conv-step.
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一个11位250MS/s子范围sar ADC在40nm CMOS
本文提出了一种11位250MS/s子范围SAR ADC。本文的子量程SAR ADC由4位flash ADC的粗转换和8位SAR ADC的细转换组成,充分结合了flash ADC的高速和SAR ADC的低功耗。本设计采用40nm低漏工艺制造,核心面积为0.018mm2。后置布局仿真在Nyquist输入下实现了9.99位的ENOB,从1.1V电源消耗1.5mW,导致FOM为5.86fJ/反步。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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