Charge effects of ultrafine FET with nanodot type floating gate

Abstract

Metal nanoparticles (NPs) embedded in junctionless field-effect transistors (JL-FETs) with a length of 3.6 nm are fabricated and demonstrated. The anisotropic wet etching of a silicon-on-insulator (SOI) substrate was utilized to form V-grooves and to define nanometer-scale channel. Metal NPs are selectively placed onto bottom of V-groove using the Bio nano process (BNP). The JL-FET is applied to floating gate memory and used to investigate an impact on the short channel by charge trap of NPs. Low-voltage operation and broad threshold voltage shift as memory behavior are appeared in 3.6 nm channel length. It is expected that the JL-FETs can overcome the scaling limitations in floating gate memory, while the charge trap cause major problems in the sub 10 nm region.