Pub Date : 2016-08-18DOI: 10.1109/AM-FPD.2016.7543622
Ming-Xun Wang, Po-Syun Chen, Chih-Lung Lin
A new stereoscopic three-dimensional (3-D) active-matrix organic light-emitting diode (AMOLED) pixel circuit composed of amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) is presented in this paper. The proposed pixel circuit has simple structure by adopting external circuit shared in one column and successfully compensates for the threshold voltage variation of a-IGZO TFTs. Therefore, the aperture ratio and brightness uniformity of displays can be ameliorated effectively. Simulation results show that the relative current error rates of the proposed pixel circuit are less than 7% over the entire input data range.
{"title":"Novel a-IGZO pixel circuit adopting external circuit for use in 3-D AMOLED displays","authors":"Ming-Xun Wang, Po-Syun Chen, Chih-Lung Lin","doi":"10.1109/AM-FPD.2016.7543622","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543622","url":null,"abstract":"A new stereoscopic three-dimensional (3-D) active-matrix organic light-emitting diode (AMOLED) pixel circuit composed of amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) is presented in this paper. The proposed pixel circuit has simple structure by adopting external circuit shared in one column and successfully compensates for the threshold voltage variation of a-IGZO TFTs. Therefore, the aperture ratio and brightness uniformity of displays can be ameliorated effectively. Simulation results show that the relative current error rates of the proposed pixel circuit are less than 7% over the entire input data range.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130633275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543620
Shih-Lun Chen, Hsin-Ju Tsai, Ting-Lan Lin, Ho-Yin Lee
In this paper, a novel hardware-oriented local dimming content adaptive backlight control (CABC) algorithm is proposed for liquid crystal displays (LCDs). It utilizes an efficient backlight dimming algorithm to reduce the power consumption of the backlight module in LCD and uses a contrast compensation algorithm to compensate the brightness distortion. In order to dim the backlight power and compensate the brightness in real time, the proposed algorithm was realized by a VLSI technique. The VLSI architecture of this design includes a grayscale converter, a maximum detector, an average calculator, a clipped point detector, a brightness compensator, a brightness ratio calculator, a ratio table and a pixel compensator. This design was synthesized by a 0.18-μm technology. Its core area and gate counts are 501,782 μm2 and 42.65-K, respectively, when it operates at 100 MHz. Compared with previous backlight control algorithms, this work improved the average PSNR value over 0.26 dB and reduced the average power consumption of LCD backlight module over 8.29%.
{"title":"Block-based content adaptive backlight controller VLSI design for local dimming LCDs","authors":"Shih-Lun Chen, Hsin-Ju Tsai, Ting-Lan Lin, Ho-Yin Lee","doi":"10.1109/AM-FPD.2016.7543620","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543620","url":null,"abstract":"In this paper, a novel hardware-oriented local dimming content adaptive backlight control (CABC) algorithm is proposed for liquid crystal displays (LCDs). It utilizes an efficient backlight dimming algorithm to reduce the power consumption of the backlight module in LCD and uses a contrast compensation algorithm to compensate the brightness distortion. In order to dim the backlight power and compensate the brightness in real time, the proposed algorithm was realized by a VLSI technique. The VLSI architecture of this design includes a grayscale converter, a maximum detector, an average calculator, a clipped point detector, a brightness compensator, a brightness ratio calculator, a ratio table and a pixel compensator. This design was synthesized by a 0.18-μm technology. Its core area and gate counts are 501,782 μm2 and 42.65-K, respectively, when it operates at 100 MHz. Compared with previous backlight control algorithms, this work improved the average PSNR value over 0.26 dB and reduced the average power consumption of LCD backlight module over 8.29%.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123119182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543633
B. Lin, Yi-Ze Hsiao, Ming-Zer Lee, Po-Cheng Tseng, Tien‐Lung Chiu, Chi-feng Lin, Jiu-Haw Lee
We demonstrated device performances of exciplex organic light emitting diodes (OLEDs) by using 4, 4', 4”-tris(N-3-methyphenyl-N-phenyl-amino) triphenylamine (m-MTDATA) and 4,7-diphenyl-1,10-phenanthroline (Bphen) as electron donor and acceptor materials, respectively with different emitting layer (EML) thicknesses. The maximum current efficiency and external quantum efficiency (EQE) of the optimized OLEDs are 11.3 cd/A and 4.02%, respectively. Transient electroluminescence (TrEL) was used to understand the carrier and exciton dynamics in the OLEDs. It was found that the thinner EML exhibited a shorter decay time in such devices.
采用4,4′，4”-三(n -3-甲基苯基- n -苯基-氨基)三苯胺(m-MTDATA)和4,7-二苯基-1,10-菲罗啉(Bphen)分别作为电子给体和受体材料，分别具有不同的发光层厚度，证明了异型有机发光二极管(oled)的器件性能。优化后的oled电流效率和外量子效率(EQE)分别为11.3 cd/A和4.02%。利用瞬态电致发光(TrEL)技术研究了oled中的载流子和激子动力学。研究发现，在这种器件中，较薄的EML表现出较短的衰减时间。
{"title":"Device performances of exciplex organic light-emitting diodes with different emitting layer thickness","authors":"B. Lin, Yi-Ze Hsiao, Ming-Zer Lee, Po-Cheng Tseng, Tien‐Lung Chiu, Chi-feng Lin, Jiu-Haw Lee","doi":"10.1109/AM-FPD.2016.7543633","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543633","url":null,"abstract":"We demonstrated device performances of exciplex organic light emitting diodes (OLEDs) by using 4, 4', 4”-tris(N-3-methyphenyl-N-phenyl-amino) triphenylamine (m-MTDATA) and 4,7-diphenyl-1,10-phenanthroline (Bphen) as electron donor and acceptor materials, respectively with different emitting layer (EML) thicknesses. The maximum current efficiency and external quantum efficiency (EQE) of the optimized OLEDs are 11.3 cd/A and 4.02%, respectively. Transient electroluminescence (TrEL) was used to understand the carrier and exciton dynamics in the OLEDs. It was found that the thinner EML exhibited a shorter decay time in such devices.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"24 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543677
Chaoyang Li, S. Hou
The gallium doped ZnO films were prepared and characterized to be used as transparent and conductive substrates replacing commercial ITO substrate applying for dye-sensitized solar cell. The thickness effects on electrical, optical and structural properties of gallium-doped ZnO films were investigated. It was found that the lowest resistivity of 3.96×10-4 Q·cm and the highest hall mobility of 14.12 cm2/(V·s) were obtained from 300 nm-thick gallium doped ZnO film as well as the high transmittance of 85% in the visible range. The demonstrated dye-sensitized solar cell used obtained gallium-doped ZnO substatrate showed the overall conversion efficiency of 1.77% with a fill factor of 0.507.
{"title":"Gallium-doped zinc oxide films as transparent and conductive substrates applying in dye-sensitized solar cell","authors":"Chaoyang Li, S. Hou","doi":"10.1109/AM-FPD.2016.7543677","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543677","url":null,"abstract":"The gallium doped ZnO films were prepared and characterized to be used as transparent and conductive substrates replacing commercial ITO substrate applying for dye-sensitized solar cell. The thickness effects on electrical, optical and structural properties of gallium-doped ZnO films were investigated. It was found that the lowest resistivity of 3.96×10-4 Q·cm and the highest hall mobility of 14.12 cm2/(V·s) were obtained from 300 nm-thick gallium doped ZnO film as well as the high transmittance of 85% in the visible range. The demonstrated dye-sensitized solar cell used obtained gallium-doped ZnO substatrate showed the overall conversion efficiency of 1.77% with a fill factor of 0.507.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543624
C. Chang, Chih-Lung Lin, Po-Syun Chen
A novel pixel circuit composed of four thin-film transistors (TFTs) and two capacitors is proposed for blue-phase liquid crystal displays (BPLCDs). The capacitive coupling method can enlarge the voltage across BPLC, and the pre-charging method shortens the charging time effectively. Four voltage levels of VBIAS are established for attaining desired voltage, when VDATA supplied by practical source driver integrated circuits (ICs) cannot reach maximum transmittance of BPLC. Simulated results based on the specification of full high-definition BPLCDs with frame rate of 180 Hz confirm that the proposed pixel circuit can enlarge the maximum operation voltage from 15 V to 30 V.
{"title":"Novel pixel circuit to enlarge operation voltage for blue-phase liquid crystal displays","authors":"C. Chang, Chih-Lung Lin, Po-Syun Chen","doi":"10.1109/AM-FPD.2016.7543624","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543624","url":null,"abstract":"A novel pixel circuit composed of four thin-film transistors (TFTs) and two capacitors is proposed for blue-phase liquid crystal displays (BPLCDs). The capacitive coupling method can enlarge the voltage across BPLC, and the pre-charging method shortens the charging time effectively. Four voltage levels of VBIAS are established for attaining desired voltage, when VDATA supplied by practical source driver integrated circuits (ICs) cannot reach maximum transmittance of BPLC. Simulated results based on the specification of full high-definition BPLCDs with frame rate of 180 Hz confirm that the proposed pixel circuit can enlarge the maximum operation voltage from 15 V to 30 V.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543688
M. Oda, K. Sakuma, Y. Kamimuta, M. Saitoh
High-performance poly-Si nano-wire transistors were fabricated by Advanced SPC process, that consists of optimized a-Si deposition, crystallization annealing and poly-Si thinning processes. In order to determine what the dominant factor of scattering mechanism is, carrier mobility behavior at each temperature and surface carrier density (Ns) are fully investigated. It reveals that the hole mobility is dominated by phonon scattering in wide Ns regime. On the other hand, it is suggested that the electron mobility is dominated by Coulomb scattering by defects inside grains at low Ns and surface roughness scattering at high Ns.
{"title":"Understanding of carrier transport in high-performance solid phase crystallized poly-Si nano-wire transistors","authors":"M. Oda, K. Sakuma, Y. Kamimuta, M. Saitoh","doi":"10.1109/AM-FPD.2016.7543688","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543688","url":null,"abstract":"High-performance poly-Si nano-wire transistors were fabricated by Advanced SPC process, that consists of optimized a-Si deposition, crystallization annealing and poly-Si thinning processes. In order to determine what the dominant factor of scattering mechanism is, carrier mobility behavior at each temperature and surface carrier density (Ns) are fully investigated. It reveals that the hole mobility is dominated by phonon scattering in wide Ns regime. On the other hand, it is suggested that the electron mobility is dominated by Coulomb scattering by defects inside grains at low Ns and surface roughness scattering at high Ns.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129050080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543663
Chin-Chiang Hsiao, M. Wei, Ting-Ting Ren, Bo-Yi Chen, Mei-Yi Li, Jui-Min Liou, F. Ko, Y. Lai
In this study, we demonstrate the high performance few-layer graphene-Si sensor with high photoresponsivity of 95 mA/W, operation behaviors with external bias as low as 0 V, and broadband operating light wavelength from 400 nm to 1000 nm by combining high transparency of few-layer graphene and n-type silicon. Although external bias benefits the photoresponsivity, the larger dark current is the price to pay. Under zero bias, the different Si substrate, n-type or p-type, provides variant Schottky barrier height guiding different photoelectrical behavior also be investigated in this work. According to the experimental results, few-layer graphene over p-type silicon (FLG p-Si) has one order higher the dark current of the few-layer graphene over n-type silicon (FLG n-Si) to ensure that the detection region between few-layer graphene and n-type silicon profits high optical-to-electrical conversion. Further, the capability of photocurrent-to-photovoltage conversion directly in one device is also provided and verified to profit the integration proposed device with periphery circuit easily.
{"title":"High optical conversion capability within the interface between graphene and Si under zero bias and visible to near infrared regime","authors":"Chin-Chiang Hsiao, M. Wei, Ting-Ting Ren, Bo-Yi Chen, Mei-Yi Li, Jui-Min Liou, F. Ko, Y. Lai","doi":"10.1109/AM-FPD.2016.7543663","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543663","url":null,"abstract":"In this study, we demonstrate the high performance few-layer graphene-Si sensor with high photoresponsivity of 95 mA/W, operation behaviors with external bias as low as 0 V, and broadband operating light wavelength from 400 nm to 1000 nm by combining high transparency of few-layer graphene and n-type silicon. Although external bias benefits the photoresponsivity, the larger dark current is the price to pay. Under zero bias, the different Si substrate, n-type or p-type, provides variant Schottky barrier height guiding different photoelectrical behavior also be investigated in this work. According to the experimental results, few-layer graphene over p-type silicon (FLG p-Si) has one order higher the dark current of the few-layer graphene over n-type silicon (FLG n-Si) to ensure that the detection region between few-layer graphene and n-type silicon profits high optical-to-electrical conversion. Further, the capability of photocurrent-to-photovoltage conversion directly in one device is also provided and verified to profit the integration proposed device with periphery circuit easily.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124613247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543689
K. Ishida, T. Meister, R. Shabanpour, B. K. Boroujeni, C. Carta, G. Cantarella, L. Petti, N. Mtozenrieder, G. Salvatore, G. Troster, F. Ellinger
This paper reviews the recent progress of active high-frequency electronics on plastic, and gives an outlook towards future advances of radio-frequency electronics in the amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistor (TFT) technology. Our a-IGZO technology is mechanically flexible, bendable and stretchable. A 0.5 μm TFT achieved a measured transit frequency of 138 MHz. We have presented several high-frequency circuits integrated in this a-IGZO technology, including several RF amplifiers and a fully-integrated AM receiver. The receiver consists of a four-stage cascode amplifier, an amplitude detector, a baseband amplifier, and a filter. At a DC current of 7.2 mA and a supply of 5 V, a conversion gain above 15dB was measured from 2 to 20MHz. Based on these works, we are investigating a wireless transmitter to be fully integrated on a plastic film. Some simulation results of a ring-oscillator based on-off-keying modulator and an LC voltage controlled oschillator under investigation are presented.
{"title":"Radio frequency electronics in a-IGZO TFT technology","authors":"K. Ishida, T. Meister, R. Shabanpour, B. K. Boroujeni, C. Carta, G. Cantarella, L. Petti, N. Mtozenrieder, G. Salvatore, G. Troster, F. Ellinger","doi":"10.1109/AM-FPD.2016.7543689","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543689","url":null,"abstract":"This paper reviews the recent progress of active high-frequency electronics on plastic, and gives an outlook towards future advances of radio-frequency electronics in the amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistor (TFT) technology. Our a-IGZO technology is mechanically flexible, bendable and stretchable. A 0.5 μm TFT achieved a measured transit frequency of 138 MHz. We have presented several high-frequency circuits integrated in this a-IGZO technology, including several RF amplifiers and a fully-integrated AM receiver. The receiver consists of a four-stage cascode amplifier, an amplitude detector, a baseband amplifier, and a filter. At a DC current of 7.2 mA and a supply of 5 V, a conversion gain above 15dB was measured from 2 to 20MHz. Based on these works, we are investigating a wireless transmitter to be fully integrated on a plastic film. Some simulation results of a ring-oscillator based on-off-keying modulator and an LC voltage controlled oschillator under investigation are presented.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123641104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543693
Takayuki Motoki, K. Yasuta, Hidenao Suzuki, Tomohiko Nakamura, M. Hasumi, T. Sameshima, T. Mizuno
A high photo-induced effective minority carrier lifetime τeff of crystalline silicon was achieved by simple heat treatment in liquid water. τeff was 2.8×10-3 s for 15-Ωcm n-type crystalline silicon heat treated in liquid water at 120°C for 1.5 h. The τeff for the sample treated at 90°C increased from 1.0×10-4 s (just after the treatment) to 1.7×10-3 s by keeping the sample in the air atmosphere for 700 h. τeff maintained high values up to 1800 h. The metal-insulator-semiconductor type diodes were formed by forming Al and Au metals on the 0.7-nm-thick passivated layers. Rectified current characteristics were observed in the dark field because of the difference of the work function between Al and Au. Capacitance response with the bias voltage suggested low density of interface traps. Short circuit current density of 24.3 mA/cm2 and open circuit voltage of 0.36 V were observed in the MIS-type solar cell under the light illumination of AM 1.5 at 100 mW/cm2 to the rear surface.
{"title":"Surface passivation of crystalline silicon by heat treatment in liquid water","authors":"Takayuki Motoki, K. Yasuta, Hidenao Suzuki, Tomohiko Nakamura, M. Hasumi, T. Sameshima, T. Mizuno","doi":"10.1109/AM-FPD.2016.7543693","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543693","url":null,"abstract":"A high photo-induced effective minority carrier lifetime τ<sub>eff</sub> of crystalline silicon was achieved by simple heat treatment in liquid water. τ<sub>eff</sub> was 2.8×10<sup>-3</sup> s for 15-Ωcm n-type crystalline silicon heat treated in liquid water at 120°C for 1.5 h. The τ<sub>eff</sub> for the sample treated at 90°C increased from 1.0×10<sup>-4</sup> s (just after the treatment) to 1.7×10<sup>-3</sup> s by keeping the sample in the air atmosphere for 700 h. τ<sub>eff</sub> maintained high values up to 1800 h. The metal-insulator-semiconductor type diodes were formed by forming Al and Au metals on the 0.7-nm-thick passivated layers. Rectified current characteristics were observed in the dark field because of the difference of the work function between Al and Au. Capacitance response with the bias voltage suggested low density of interface traps. Short circuit current density of 24.3 mA/cm<sup>2</sup> and open circuit voltage of 0.36 V were observed in the MIS-type solar cell under the light illumination of AM 1.5 at 100 mW/cm<sup>2</sup> to the rear surface.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-06DOI: 10.1109/AM-FPD.2016.7543607
T. Ban, S. Migita, Y. Uraoka, Shin-ichi Yamamoto
Metal nanoparticles (NPs) embedded in junctionless field-effect transistors (JL-FETs) with a length of 3.6 nm are fabricated and demonstrated. The anisotropic wet etching of a silicon-on-insulator (SOI) substrate was utilized to form V-grooves and to define nanometer-scale channel. Metal NPs are selectively placed onto bottom of V-groove using the Bio nano process (BNP). The JL-FET is applied to floating gate memory and used to investigate an impact on the short channel by charge trap of NPs. Low-voltage operation and broad threshold voltage shift as memory behavior are appeared in 3.6 nm channel length. It is expected that the JL-FETs can overcome the scaling limitations in floating gate memory, while the charge trap cause major problems in the sub 10 nm region.
{"title":"Charge effects of ultrafine FET with nanodot type floating gate","authors":"T. Ban, S. Migita, Y. Uraoka, Shin-ichi Yamamoto","doi":"10.1109/AM-FPD.2016.7543607","DOIUrl":"https://doi.org/10.1109/AM-FPD.2016.7543607","url":null,"abstract":"Metal nanoparticles (NPs) embedded in junctionless field-effect transistors (JL-FETs) with a length of 3.6 nm are fabricated and demonstrated. The anisotropic wet etching of a silicon-on-insulator (SOI) substrate was utilized to form V-grooves and to define nanometer-scale channel. Metal NPs are selectively placed onto bottom of V-groove using the Bio nano process (BNP). The JL-FET is applied to floating gate memory and used to investigate an impact on the short channel by charge trap of NPs. Low-voltage operation and broad threshold voltage shift as memory behavior are appeared in 3.6 nm channel length. It is expected that the JL-FETs can overcome the scaling limitations in floating gate memory, while the charge trap cause major problems in the sub 10 nm region.","PeriodicalId":422453,"journal":{"name":"2016 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127372881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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