A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

Abstract

Continued scaling of the transistor increases random Vt variation, which limits the minimum operating voltage $(V_{\mathrm{MIN}})$. Furthermore, fin formation differences between the SRAM bitcells, the peripheral circuits and the standard logic degrade area efficiency due to the empty spaces at fin-to-fin boundary and the required dummy [1]. Memories with small capacities that use the classical SRAM design suffer from this issue the most. In this paper, we will propose a 5nm digital-based SRAM macro with a 16T cell supporting a bit-write-mask operation. We adopted the standard cell rules for the proposed SRAM layout design. The area of the 16T cell is larger than the foundry’s 6T SRAM cell; however, the total macro area of a small capacity SRAM is smaller since there is no empty space in the macro and due to its simple peripheral circuit. In addition, the proposed SRAM can be directly abutted with the standard cell region. The proposed SRAM can support ultra-wide range voltage operation due to the advantages of a digital-based bitcell design.