{"title":"Ultra low leakage 90nm content addressable memory design for wireless sensor network applications","authors":"Swaran R. Singh, K. Moez","doi":"10.1109/MWSCAS.2009.5235948","DOIUrl":null,"url":null,"abstract":"Wireless sensor networks are emerging as a compelling solution for a diverse range of data gathering applications. The constituent sensor nodes in these networks typically run on unreplenishable battery supplies, thereby placing energy at a premium. Ultra-low power content addressable memory is required to implement the routing caches for many network protocols used in wireless sensor networks. This paper investigates several circuit techniques for reducing leakage currents in content addressable memories on a 90nm process. Simulations show that leakage currents in a 4kbit memory array can by reduced by a factor of 168x relative to a conventional, unoptimized design.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2009.5235948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Wireless sensor networks are emerging as a compelling solution for a diverse range of data gathering applications. The constituent sensor nodes in these networks typically run on unreplenishable battery supplies, thereby placing energy at a premium. Ultra-low power content addressable memory is required to implement the routing caches for many network protocols used in wireless sensor networks. This paper investigates several circuit techniques for reducing leakage currents in content addressable memories on a 90nm process. Simulations show that leakage currents in a 4kbit memory array can by reduced by a factor of 168x relative to a conventional, unoptimized design.