Qualitative and quantitative evaluation of a proposed circuit switched network-on-chip

Abstract

The advancement of semiconductor industry has led to continuously increasing level of integration. Due to this and driven by shorter time-to-market and product life cycle, the industry has migrated into SoC paradigm. NoC is viewed as a practical solution for SoC interconnection due to its reusability and scalability. Existing NoC designs are mainly based on packet switching. However, packet switching NoC requires significant buffering resources, which consumes silicon area and power. An alternative to packet switching is circuit switching based NoC. In this paper, a circuit switched network protocol and NoC design had been proposed and evaluated both qualitatively and quantitatively. Simulations were performed to measure and compare the performance of both NoCs to determine the viability of CNoC as on-chip interconnection solution.