Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results

Abstract

In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.