Integration of high-level modeling, formal verification, and high-level synthesis in ATM switch design

Abstract

We present a high-level ATM switch design methodology, beginning with parametric high-level model, debugging the model using a combination of formal verification and simulation, and synthesizing the model to a gate-level implementation. Our parametric model of an ATM switch has been used to automatically synthesize ATM switches of customers' choices by choosing concrete values of the generic parameters. The difficulty in validating ATM switch design arises not only due to parametrization, but also due to delicate control module design involved in concurrent processes communicating through shared signals. We provide a pragmatic combination of simulation, model checking, and theorem proving to gain confidence in the correctness of ATM switch design.