M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga
{"title":"A CMOS 12K gate array with flexible 10Kb memory","authors":"M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga","doi":"10.1109/ISSCC.1984.1156670","DOIUrl":null,"url":null,"abstract":"A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156670","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.
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