A novel approach for ESD-immunity analysis using channel transfer impedance on the power delivery network of a large-scale integration chip

S. Moon, Jihyun Lee, Jaeyoul Lee
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引用次数: 1

Abstract

In this work, we proposed a novel approach for electrostatic discharge (ESD) noise stress analysis using transfer impedance analysis in a platform for a large-scale integration chip. In the electronic industry an ESD test is widely taken to evaluate the noise immunity of a designed electronic device. In this ESD test, critical hardware damage or functional problems may occur due to temporary electrical disturbances produced by applying an external electrical shock. By manipulating the transfer-impedance difference from a noise-induced point to power/ground points of an IC, the influence of an induced ESD noise that could significantly affect the IC's performance was analyzed. The ESD noise stress affects supply voltage to become unstable in a power delivery network (PDN) and adversely affects analog/digital circuit operations during data processing. The impedance differences in the PDN produces supply voltage instability in a designed chip. Thus, by analyzing the transfer impedance from the PCB to the power nets of a time-controller IC, the variation of supply voltage due to external ESD noise can be estimated. In order to separate noise-to-power and noise-to-ground paths on a PCB, an additional ground layer, which exists only in simulation, was used for estimating temporal voltage fluctuation due to impedance imbalance between the noise-to-power and the noise-to-ground paths. In comparison, the proposed approach was demonstrated to agree with the measurement up to 500 MHz. This estimation result indicated that the simulation approach on ESD noise immunity using transfer impedance is useful to predict the influence of electrical stress to a designed IC on a PCB. The estimation approach on ESD noise impact is expected to be applicable for the PDN design of a PCB/IC to improve its ESD noise immunity prior to its implementation.
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一种基于大规模集成芯片供电网络通道传输阻抗的抗静电分析新方法
在这项工作中,我们提出了一种在大规模集成芯片平台上使用传递阻抗分析进行静电放电(ESD)噪声应力分析的新方法。在电子工业中,ESD测试被广泛用于评估设计的电子设备的抗噪声性。在此测试中,外部电击可能会产生暂时的电气干扰,从而导致硬件损坏或功能问题。通过控制IC从噪声诱发点到功率/接地点的传输阻抗差,分析了可显著影响IC性能的诱导ESD噪声的影响。在PDN (power delivery network)中,ESD噪声应力会导致供电电压变得不稳定,并对数据处理过程中的模拟/数字电路的运行产生不利影响。在设计的芯片中,PDN中的阻抗差会产生电源电压不稳定。因此,通过分析从PCB到时间控制器IC的电网的传输阻抗,可以估计由于外部ESD噪声引起的电源电压变化。为了分离PCB上的噪声到功率路径和噪声到地路径,使用仅在仿真中存在的附加接地层来估计由于噪声到功率路径和噪声到地路径之间的阻抗不平衡而引起的时间电压波动。通过比较,证明了所提出的方法与高达500 MHz的测量一致。这一估计结果表明,基于传递阻抗的ESD抗扰度仿真方法有助于预测电应力对PCB上设计的集成电路的影响。ESD噪声影响的估计方法有望应用于PCB/IC的PDN设计,以提高其实施前的ESD抗扰性。
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