An Efficient Reconfigurable Image Compression Architecture

Abstract

This paper describes the development of a novel image compression architecture on runtime reconfigurable FPGAs. The partially reconfigurable discrete cosine transform architecture (PRDCT) is implemented by creating a difference bit stream between two possible architectures using flexible multiplier and accumulator (MAC) units. The non-reconfigurable modules make use of a multiplexed bus system to communicate with the reconfigurable modules. This scheme helps the user achieve significant reduction in area and power during run-time