High-level area prediction for power estimation

Abstract

High-level power estimation, when given only a high level design specification such as a functional or RTL description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the area complexity of single-output Boolean functions given only their functional description, where area complexity is measured in terms of the number of gates required for an optimal implementation of the function. We propose an area model that makes use of a new complexity measure. The model is empirical, and is based on an observed relationship between the proposed complexity measure, which is easily measurable using Monte-Carlo simulation, and its optimal implementation (gate-count). This model has been implemented, and empirical results demonstrating its feasibility and utility are presented.