Design of very low power time — domain analog — to — digital converter

Abstract

In this work design of a highly digital intensive Analog-to-Digital Converter is proposed using UMC 180 nm CMOS process technology with 1.8 V power supply. The ADC gives 5-bit resolution for a sampling frequency of 16.11 MHz while occupying 0.012 mm2 area. Average power consumption is only 1.43 mW. The design is implemented using a single-phase VCO based quantizer. The VCO has a clock-to-clock jitter of 769 fs and the frequency counter, that has been used as quantizer, is compatible with frequencies in the GHz range.