Parasitics effects in multi gate MOSFETs

Abstract

The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies. Using extensive 3-D device and circuit simulations, the impact of parasitics on the device and circuit performance is systematically investigated. The results clearly identify the issues in integrating high-K gate dielectrics in scaled multi-gate transistors. We show from 3-D simulations that, when a high-K gate dielectric (with a K ~ 15, similar to hafnium oxide) is integrated in a multi-gate transistor, a 5times increase (compared to the SiO2) in the off current occurs due to the fringing field induced barrier lowering effects. At the circuit level, our results show that, an order of magnitude degradation in the delay can take place, due to the unoptimized FinFET layouts.