Pub Date : 2008-07-22DOI: 10.1109/IWNC.2006.4570999
J. Tonotani
Summary form given only: A stacked film structure of lanthanum oxide and silicon (La2O3/Si) is considered to be used in MOSFETs in the Nano-CMOS era since La2O3 is a promising high-k gate insulator. In the substrate contact formation process, La2O3 should be removed selectively against Si substrate. In order to examine the possibility of the selective dry etching of La2O3/Si stacked film, dry etching characteristics of La2O3 and Si were investigated. As a result, it was found that pure Ar sputtering as well as an addition of Cl2, BCl3 or CF4 to Ar caused higher etching rate of Si than that of La2O3, which led to a low etching selectivity. In Ar plasma in a chamber with B contaminations, however, Si was not etched while La2O3 was etched with the etching rate about 2 nm/min. X-ray photoelectron spectroscopy revealed that B existed only on the etched Si surface, which was considered effective for preventing Si from being etched by Ar sputtering. As a conclusion, noble gas plasma, such as Ar plasma, with small amount of B fluxes to the etching surface enables the La2O3/Si selective etching.
{"title":"Selective dry etching of La2O3/Si stacked film","authors":"J. Tonotani","doi":"10.1109/IWNC.2006.4570999","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570999","url":null,"abstract":"Summary form given only: A stacked film structure of lanthanum oxide and silicon (La<sub>2</sub>O<sub>3</sub>/Si) is considered to be used in MOSFETs in the Nano-CMOS era since La<sub>2</sub>O<sub>3</sub> is a promising high-k gate insulator. In the substrate contact formation process, La<sub>2</sub>O<sub>3</sub> should be removed selectively against Si substrate. In order to examine the possibility of the selective dry etching of La<sub>2</sub>O<sub>3</sub>/Si stacked film, dry etching characteristics of La<sub>2</sub>O<sub>3</sub> and Si were investigated. As a result, it was found that pure Ar sputtering as well as an addition of Cl<sub>2</sub>, BCl<sub>3</sub> or CF<sub>4</sub> to Ar caused higher etching rate of Si than that of La<sub>2</sub>O<sub>3</sub>, which led to a low etching selectivity. In Ar plasma in a chamber with B contaminations, however, Si was not etched while La<sub>2</sub>O<sub>3</sub> was etched with the etching rate about 2 nm/min. X-ray photoelectron spectroscopy revealed that B existed only on the etched Si surface, which was considered effective for preventing Si from being etched by Ar sputtering. As a conclusion, noble gas plasma, such as Ar plasma, with small amount of B fluxes to the etching surface enables the La<sub>2</sub>O<sub>3</sub>/Si selective etching.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134186619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1093/ietele/e90-c.10.2051
Yusuke Kobayashi, C. R. Manoj, K. Tsutsui, Venkanarayan Hariharan, K. Kakushima, V. Rao, P. Ahmet, H. Iwai
The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies. Using extensive 3-D device and circuit simulations, the impact of parasitics on the device and circuit performance is systematically investigated. The results clearly identify the issues in integrating high-K gate dielectrics in scaled multi-gate transistors. We show from 3-D simulations that, when a high-K gate dielectric (with a K ~ 15, similar to hafnium oxide) is integrated in a multi-gate transistor, a 5times increase (compared to the SiO2) in the off current occurs due to the fringing field induced barrier lowering effects. At the circuit level, our results show that, an order of magnitude degradation in the delay can take place, due to the unoptimized FinFET layouts.
{"title":"Parasitics effects in multi gate MOSFETs","authors":"Yusuke Kobayashi, C. R. Manoj, K. Tsutsui, Venkanarayan Hariharan, K. Kakushima, V. Rao, P. Ahmet, H. Iwai","doi":"10.1093/ietele/e90-c.10.2051","DOIUrl":"https://doi.org/10.1093/ietele/e90-c.10.2051","url":null,"abstract":"The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies. Using extensive 3-D device and circuit simulations, the impact of parasitics on the device and circuit performance is systematically investigated. The results clearly identify the issues in integrating high-K gate dielectrics in scaled multi-gate transistors. We show from 3-D simulations that, when a high-K gate dielectric (with a K ~ 15, similar to hafnium oxide) is integrated in a multi-gate transistor, a 5times increase (compared to the SiO2) in the off current occurs due to the fringing field induced barrier lowering effects. At the circuit level, our results show that, an order of magnitude degradation in the delay can take place, due to the unoptimized FinFET layouts.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127596952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570986
Ji Chen, J. Liou
In this paper, a physics-based model applicable for CMOS technology-based inductors will be developed. Our model development will cover both the symmetrical and asymmetrical inductors. In addition, an octagonal spiral pattern will be considered, but the approach applies generally to other non-circular patterns.
{"title":"CMOS technology-based spiral inductors for RF applications","authors":"Ji Chen, J. Liou","doi":"10.1109/IWNC.2006.4570986","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570986","url":null,"abstract":"In this paper, a physics-based model applicable for CMOS technology-based inductors will be developed. Our model development will cover both the symmetrical and asymmetrical inductors. In addition, an octagonal spiral pattern will be considered, but the approach applies generally to other non-circular patterns.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126749736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570972
Y. Nishi
Scaling trend of CMOS, coupled with possibility of new channel materials, metal gate/ high k gate stack and source/drain structures is discussed, followed by several possibilities and opportunities for non-silicon devices including new material based non-volatile memory devices.
{"title":"CMOS scaling and non-silicon opportunities","authors":"Y. Nishi","doi":"10.1109/IWNC.2006.4570972","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570972","url":null,"abstract":"Scaling trend of CMOS, coupled with possibility of new channel materials, metal gate/ high k gate stack and source/drain structures is discussed, followed by several possibilities and opportunities for non-silicon devices including new material based non-volatile memory devices.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570975
E. Sangiorgi, N. Barin, M. Braccioli, C. Fiegna
State of the art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the Ultra-Thin Silicon Body Double-Gate (UTB-DG) MOSFET. n-MOSFETs designed according to an original scaling strategy are simulated and the main figures of merit of the high-performance MOS transistor for digital applications are evaluated and compared to the requirements of the International Technology Roadmap for Semiconductors.The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field.
{"title":"32nm technology node Double-Gate SOI MOSFET using SiO2 gate stacks","authors":"E. Sangiorgi, N. Barin, M. Braccioli, C. Fiegna","doi":"10.1109/IWNC.2006.4570975","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570975","url":null,"abstract":"State of the art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the Ultra-Thin Silicon Body Double-Gate (UTB-DG) MOSFET. n-MOSFETs designed according to an original scaling strategy are simulated and the main figures of merit of the high-performance MOS transistor for digital applications are evaluated and compared to the requirements of the International Technology Roadmap for Semiconductors.The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"23 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120984848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570998
S. Cristoloveanu
Without SOI, the future of the microelectronics would be hopeless and the CMOS technology would be useless. SOI does not mean Silicon On Insulator, it comprises any kind of semiconductor, strained or not, on any type of dielectric, with the stringent condition to have ultra-thin layers. This is why the scaling of MOS transistors is intrinsically easier in SOI than in bulk Si, where it is becoming a desperate issue. The nano-size MOS transistor stands as the perfect device for the natural transition from microelectronics to nanoelectronics. In addition, SOI is a most suitable substrate for the implementation of non-classic or pure nanoelectronic components. The dimensions of state-of-the-art SOI MOSFETs are already measurable in nanometers. The aim of this presentation is to illustrate, from an experimental viewpoint, a number of nano-size mechanisms and implications. The scaling beyond 10-nm channel-length is discussed by addressing the main effects: fringing fields, self-heating, transition from partial to full depletion, etc. A good electrostatic control requires nanometer-thick SOI films, where yet another family of mechanisms takes place: super-coupling, volume inversion, and quantization. Finally, the shrinking of the device width enables quantum wire operation and lateral strain or doping effects. A key aspect is that all dimensions need to be reduced concomitantly, not separately. An ultimate SOI MOSFET should be viewed and modelled as a transistor with a miniaturized volume. This is particularly true for innovative devices with multiple gates and/or non-planar configuration. Two, three or four gates can collaborate to bring enhanced performance, functionality, flexibility and scaling. Several device architectures will be evaluated by comparing their merits and ease of processing. Since the device operation is governed by 3-D effects, we will focus on the coupling between the longitudinal, lateral and vertical directions.
{"title":"Length, width and thickness effects in SOI transistors","authors":"S. Cristoloveanu","doi":"10.1109/IWNC.2006.4570998","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570998","url":null,"abstract":"Without SOI, the future of the microelectronics would be hopeless and the CMOS technology would be useless. SOI does not mean Silicon On Insulator, it comprises any kind of semiconductor, strained or not, on any type of dielectric, with the stringent condition to have ultra-thin layers. This is why the scaling of MOS transistors is intrinsically easier in SOI than in bulk Si, where it is becoming a desperate issue. The nano-size MOS transistor stands as the perfect device for the natural transition from microelectronics to nanoelectronics. In addition, SOI is a most suitable substrate for the implementation of non-classic or pure nanoelectronic components. The dimensions of state-of-the-art SOI MOSFETs are already measurable in nanometers. The aim of this presentation is to illustrate, from an experimental viewpoint, a number of nano-size mechanisms and implications. The scaling beyond 10-nm channel-length is discussed by addressing the main effects: fringing fields, self-heating, transition from partial to full depletion, etc. A good electrostatic control requires nanometer-thick SOI films, where yet another family of mechanisms takes place: super-coupling, volume inversion, and quantization. Finally, the shrinking of the device width enables quantum wire operation and lateral strain or doping effects. A key aspect is that all dimensions need to be reduced concomitantly, not separately. An ultimate SOI MOSFET should be viewed and modelled as a transistor with a miniaturized volume. This is particularly true for innovative devices with multiple gates and/or non-planar configuration. Two, three or four gates can collaborate to bring enhanced performance, functionality, flexibility and scaling. Several device architectures will be evaluated by comparing their merits and ease of processing. Since the device operation is governed by 3-D effects, we will focus on the coupling between the longitudinal, lateral and vertical directions.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134464368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570984
Y. Nara, S. Inumiya, S. Kamiyama, Kunio Nakamura
This proceeding we will discuss the scalability of Hf-based high-k gate dielectrics for hp45 node and beyond both with high-temperature gate-first integration and low-temperature gate-last integration. It describes the process optimization and metal gate MOSFET characteristics using gate-first integration with HfSiON and gate-last integration with HfO2.
{"title":"Hf-based high-k gate dielectrics - Scalability for hp45 node and beyond -","authors":"Y. Nara, S. Inumiya, S. Kamiyama, Kunio Nakamura","doi":"10.1109/IWNC.2006.4570984","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570984","url":null,"abstract":"This proceeding we will discuss the scalability of Hf-based high-k gate dielectrics for hp45 node and beyond both with high-temperature gate-first integration and low-temperature gate-last integration. It describes the process optimization and metal gate MOSFET characteristics using gate-first integration with HfSiON and gate-last integration with HfO2.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133009419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570988
K. Ohmori, P. Ahmet, K. Shiraishi, H. Watanabe, Y. Akasaka, K. Yamabe, M. Yoshitake, K. Chang, M. Green, K. Yamada, T. Chikyow
This paper reports a systematic investigation of flatband voltage (Vfb), properties for HfO2-SiO2-Si capacitors using metal alloy electrodes of Pt-W alloy as a means of tuning work function (WF). It was found that the value of Vfb, for W (lower WF) is retained after forming gas annealing (FGA) and oxidizing gas annealing (OGA) processes, while that for Pt (higher WF) strongly depends on the annealing condition. The difference in Vfb, between Pt and W is 0.34 V at most, which is smaller compared with the WF difference of 0.8 eV.
{"title":"Influences of annealing conditions on flatband voltage properties using continuously workfunction-tuned metal electrodes","authors":"K. Ohmori, P. Ahmet, K. Shiraishi, H. Watanabe, Y. Akasaka, K. Yamabe, M. Yoshitake, K. Chang, M. Green, K. Yamada, T. Chikyow","doi":"10.1109/IWNC.2006.4570988","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570988","url":null,"abstract":"This paper reports a systematic investigation of flatband voltage (Vfb), properties for HfO2-SiO2-Si capacitors using metal alloy electrodes of Pt-W alloy as a means of tuning work function (WF). It was found that the value of Vfb, for W (lower WF) is retained after forming gas annealing (FGA) and oxidizing gas annealing (OGA) processes, while that for Pt (higher WF) strongly depends on the annealing condition. The difference in Vfb, between Pt and W is 0.34 V at most, which is smaller compared with the WF difference of 0.8 eV.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570978
K. Tsutsui, Y. Sasaki, K. Majima, Y. Fukagawa, I. Aiba, R. Higaki, C. Jin, H. Ito, B. Mizuno, J. Ng, K. Tachi, Jaeyeol Song, Y. Shiino, K. Kakushima, P. Ahmet, H. Iwai
In this work, combination of the plasma doping method with flush lamp annealing (FLA) or solid-state laser annealing (ASLA) is shown to be very promising technique to form ultra-shallow and low-resistive junctions for future nano CMOS. Amorphisation by He plasma (He-PA process) is shown to be effective for obtaining shallow junction depth (Xj) and low sheet resistance (Rs). The He-PA process is found to contribute to the increase of sheet charier concentration, which governs the sheet resistances as revealed by Hall measurements. However, even if these techniques are used, activation rate under the annealing conditions to keep shallow Xj is still low, thus, further investigation to improve the carrier activation is necessary. The junction leakage for the ultra-shallow Si P/N junction diodes formed by plasma doping of boron is examined, and it was shown to be as low as that formed by the low energy ion implantation. Feasibility study of La2O3 gate oxide of MOS capacitors and MOSFET is presented. The effect of annealing temperature on the effective mobility is investigated been obtained and shows strong correlation of the mobility and interface states. Insertion of Y2O3 or Sc2O3 at La2O3/Si interface suppresses the increase of EOT after the annealing.
{"title":"Ultra-shallow junction and high-k dielectric for Nano CMOS","authors":"K. Tsutsui, Y. Sasaki, K. Majima, Y. Fukagawa, I. Aiba, R. Higaki, C. Jin, H. Ito, B. Mizuno, J. Ng, K. Tachi, Jaeyeol Song, Y. Shiino, K. Kakushima, P. Ahmet, H. Iwai","doi":"10.1109/IWNC.2006.4570978","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570978","url":null,"abstract":"In this work, combination of the plasma doping method with flush lamp annealing (FLA) or solid-state laser annealing (ASLA) is shown to be very promising technique to form ultra-shallow and low-resistive junctions for future nano CMOS. Amorphisation by He plasma (He-PA process) is shown to be effective for obtaining shallow junction depth (Xj) and low sheet resistance (Rs). The He-PA process is found to contribute to the increase of sheet charier concentration, which governs the sheet resistances as revealed by Hall measurements. However, even if these techniques are used, activation rate under the annealing conditions to keep shallow Xj is still low, thus, further investigation to improve the carrier activation is necessary. The junction leakage for the ultra-shallow Si P/N junction diodes formed by plasma doping of boron is examined, and it was shown to be as low as that formed by the low energy ion implantation. Feasibility study of La2O3 gate oxide of MOS capacitors and MOSFET is presented. The effect of annealing temperature on the effective mobility is investigated been obtained and shows strong correlation of the mobility and interface states. Insertion of Y2O3 or Sc2O3 at La2O3/Si interface suppresses the increase of EOT after the annealing.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131922072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570992
K. Shiraishi, Y. Akasaka, K. Torii, T. Nakayama, S. Miyazaki, T. Nakaoka, H. Watanabe, K. Ohmori, P. Ahmet, T. Chikyow, Y. Nara, K. Yamada
We show the new findings in nano-scale interface physics and atomistic behaviors of defects in gate dielectric materials. In this paper, we first discuss the relation between defect behaviors and transistor characteristics. Next, we introduce our newly prosed mechanism of Fermi level pinning governed by the interface reaction. Further, we show that conventional charge neutrality level concept does not applicable to metal/high-k dielectric interfaces, and we propose a generalized charge neutrality level concept that includes both nano-scale interface structures and metal band structures. Finally, we discuss the atomistic investigation on the characteristics of conventional Si/SiO2 nano interfaces.
{"title":"New findings in nano-scale interface physics and their relations to nano-CMOS technologies","authors":"K. Shiraishi, Y. Akasaka, K. Torii, T. Nakayama, S. Miyazaki, T. Nakaoka, H. Watanabe, K. Ohmori, P. Ahmet, T. Chikyow, Y. Nara, K. Yamada","doi":"10.1109/IWNC.2006.4570992","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570992","url":null,"abstract":"We show the new findings in nano-scale interface physics and atomistic behaviors of defects in gate dielectric materials. In this paper, we first discuss the relation between defect behaviors and transistor characteristics. Next, we introduce our newly prosed mechanism of Fermi level pinning governed by the interface reaction. Further, we show that conventional charge neutrality level concept does not applicable to metal/high-k dielectric interfaces, and we propose a generalized charge neutrality level concept that includes both nano-scale interface structures and metal band structures. Finally, we discuss the atomistic investigation on the characteristics of conventional Si/SiO2 nano interfaces.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132941178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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