Architecture driven computational ordering and code generation method for DSP compiler

Abstract

A computational ordering and code generation method for DSP compiler, which take the target DSP architecture, i.e., the number of accumulators, bus structure and multi-operation instruction code, into consideration is proposed. By combining computation ordering and code generation into one step, a better outcome code of DSP compiler may be obtained. Although only /spl mu/PD 7720 is used as target DSP in this work, the method may be applied to other DSPs.