{"title":"CAD flows for chip-package codesign","authors":"A. Varma, A. Glaser, P. Franzon","doi":"10.1109/EPEP.2003.1249989","DOIUrl":null,"url":null,"abstract":"A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2003.1249989","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.
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