Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator

Abstract

In Internet of Things (IOT) based applications, security is given the highest importance and cryptography plays a major role in maintaining the data safety. Encryption and decryption in cryptography requires a Pseudo random bit generator (PRBG) for key generation. Modified dual coupled linear congruential generator (MDCLCG) based PRBG is the highly efficient PRBG algorithm as it clears a1115 National Institute of Standards and Technology (NIST) tests and has maximum period of 2n for a n-bit design. In this paper, complete design and testing of a 64-bit MDCLCG based PRBG is proposed and it’s implementation on Kintex-7 XC7K160TFBG676-3 field-programmable gate array (FPGA) is presented. Main components of MDCLCG based PRBG includes a Three operand adder, Barrel shifter, Comparator and an Encoder. Further, a High speed area efficient three operand adder (HSAEA) is used to improve performance of the proposed 64-bit MDCLCG architecture. It’s performance is compared with 64-bit MDCLCG designed using three operand Ultra fast adder (UFA) and three operand Carry save adder (CSA) architectures. The post-implementation results of the proposed 64-bit MDCLCG are carried out and from the analysis, it is reported that the proposed 64-bit MDCLCG designed using HSAEA has 25.1%, 9.2% reduction in Area/Maximum frequency $(A/F_{Max})$ value when compared to UFA and CSA based 64-bit MDCLCG architectures respectively. Also, it has 17.7%, 4.4% reduction in Power/Maximum frequency $(P/F_{Max})$ value over UFA and CSA based 64-bit MDCLCG architectures respectively. Moreover, the proposed 64-bit MDCLCG ensures more security than 32-bit MDCLCG proposed in literature as the pseudo random bit sequence has a period of 264 bits instead of 232 bits.