Design and Simulation of Fault Tolerances in Combinational Circuits Using CMOS 45nm Technology

Abstract

In this paper,. As we designed complexity circuit there may be any errors or faults. The faults may be stuck at ‘0’, stuck at ‘1'or may be a bridge fault. In order to identify the fault or error in circuit we need to verify each and every block to identify whether error or fault occurred. So to decrease the complexity of circuit and to identify error once after the design of circuit is completed. So to overcome the faults in circuit we are using self-checking multiplexer. Here we are designing self- repairing 2:1 multiplexer. By designing this circuit we can find and repair all kind of faults. In this paper proposing two methods in that the first method is detected and correct fault in Mux. Detect and correct faults in basic gates. New models can give 100% error accuracy. To design the proposed fast full adder here we are using hybrid logic style. This proposed method has been designed and analyzed using CMOS Mentor graphics 45nm Technology.