{"title":"The Rambus memory system","authors":"J.A. Gasbarro","doi":"10.1109/MTDT.1995.518088","DOIUrl":null,"url":null,"abstract":"This paper describes a revolutionary new technology for building high-performance DRAM memory systems that operate up to 10 times faster than conventional systems. With only a 9-bit wide interface, devices are capable of transferring data at over 500 MBytes per second. This technology is implemented using standard CMOS process, packaging and printed circuit fabrication techniques, and is suitable for cost-sensitive volume applications.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1995.518088","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper describes a revolutionary new technology for building high-performance DRAM memory systems that operate up to 10 times faster than conventional systems. With only a 9-bit wide interface, devices are capable of transferring data at over 500 MBytes per second. This technology is implemented using standard CMOS process, packaging and printed circuit fabrication techniques, and is suitable for cost-sensitive volume applications.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
