Low-latency software LDPC decoders for x86 multi-core devices

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI:10.1109/SiPS.2017.8110001

B. Gal, C. Jégo

引用次数: 9

Abstract

LDPC codes are a family of error correcting codes used in most modern digital communication standards even in future 3GPP 5G standard. Thanks to their high processing power and their parallelization capabilities, prevailing multi-core and many-core devices facilitate real-time implementations of digital communication systems, which were previously implemented on dedicated hardware targets. Through massive frame decoding parallelization, current LDPC decoders throughputs range from hundreds of Mbps up to Gbps. However, inter-frame parallelization involves latency penalties, while in future 5G wireless communication systems, the latency should be reduced as far as possible. To this end, a novel LDPC parallelization approach for LDPC decoding on a multi-core processor device is proposed in this article. It reduces the processing latency down to some microseconds as highlighted by x86 multi-core experimentations.

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用于x86多核设备的低延迟软件LDPC解码器

LDPC码是大多数现代数字通信标准甚至未来3GPP 5G标准中使用的纠错码族。由于它们的高处理能力和并行化能力，流行的多核和多核设备促进了数字通信系统的实时实现，而这些系统以前是在专用硬件目标上实现的。通过大规模帧解码并行化，目前的LDPC解码器吞吐量从数百Mbps到Gbps不等。然而，帧间并行涉及延迟损失，而在未来的5G无线通信系统中，延迟应尽可能减少。为此，本文提出了一种在多核处理器设备上实现LDPC并行解码的新方法。它将处理延迟降低到几微秒，正如x86多核实验所突出显示的那样。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2017 IEEE International Workshop on Signal Processing Systems (SiPS)

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