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2017 IEEE International Workshop on Signal Processing Systems (SiPS)最新文献

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Hardware error correction using local syndromes 使用局部症候群进行硬件纠错
Pub Date : 2017-10-03 DOI: 10.1109/SiPS.2017.8109995
Mohamed Mourad Hafidhi, E. Boutillon
Increasing the integration density offers the possibility for designers to built very complex system on a single chip. However, approaching the limits of integration, circuit reliability has emerged as a critical concern. The loss of reliability increases with process/voltage and temperature (PVT) variations. Faults can appear in circuits which can affect the system behaviour and lead to a system failure. Therefore it is increasingly important to build more fault tolerant resilient system. This paper 1 proposes a new fault tolerant scheme, the Duplication with Syndrome based Correction (DSC) scheme. Two criteria were considered to evaluate the proposed scheme: the reliability (probability that no error appears in the output of the architecture) and the hardware efficiency of the architecture. Results show that the DSC scheme reduces the complexity by 32%, compared to the classical Triple Modular Redundancy (TMR) scheme, while maintaining a level of reliability closed to the TMR. The paper shows also an example of signal processing applications where the DSC has been used to protect the correlation function and filters inside the tracking loops of the Global Positioning System (GPS) receiver.
提高集成密度为设计人员在单个芯片上构建非常复杂的系统提供了可能性。然而,接近集成的极限,电路可靠性已成为一个关键问题。可靠性损失随着工艺/电压和温度(PVT)的变化而增加。故障可能出现在电路中,影响系统行为并导致系统故障。因此,构建容错能力更强的弹性系统变得越来越重要。本文提出了一种新的容错方案——基于综合征的复制校正(DSC)方案。考虑了两个标准来评估所提出的方案:可靠性(体系结构输出中不出现错误的概率)和体系结构的硬件效率。结果表明,与经典的三模冗余(TMR)方案相比,DSC方案将复杂性降低了32%,同时保持了接近TMR的可靠性水平。文中还举例说明了DSC在全球定位系统(GPS)接收机跟踪回路中用于保护相关函数和滤波器的信号处理应用。
{"title":"Hardware error correction using local syndromes","authors":"Mohamed Mourad Hafidhi, E. Boutillon","doi":"10.1109/SiPS.2017.8109995","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109995","url":null,"abstract":"Increasing the integration density offers the possibility for designers to built very complex system on a single chip. However, approaching the limits of integration, circuit reliability has emerged as a critical concern. The loss of reliability increases with process/voltage and temperature (PVT) variations. Faults can appear in circuits which can affect the system behaviour and lead to a system failure. Therefore it is increasingly important to build more fault tolerant resilient system. This paper 1 proposes a new fault tolerant scheme, the Duplication with Syndrome based Correction (DSC) scheme. Two criteria were considered to evaluate the proposed scheme: the reliability (probability that no error appears in the output of the architecture) and the hardware efficiency of the architecture. Results show that the DSC scheme reduces the complexity by 32%, compared to the classical Triple Modular Redundancy (TMR) scheme, while maintaining a level of reliability closed to the TMR. The paper shows also an example of signal processing applications where the DSC has been used to protect the correlation function and filters inside the tracking loops of the Global Positioning System (GPS) receiver.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design space exploration of dataflow-based Smith-Waterman FPGA implementations 基于数据流的Smith-Waterman FPGA实现的设计空间探索
Pub Date : 2017-10-03 DOI: 10.1109/SiPS.2017.8109982
S. Brunet, E. Bezati, M. Mattavelli
The paper presents the results of design space explorations for the implementation of the Smith-Waterman (S-W) algorithm performing DNA and protein sequences alignment. Both design explorations studies and FPGA implementations are obtained by developing a dynamic dataflow program implementing the algorithm and by direct high-level synthesis (HLS) to FPGA HDL. The main feature of the obtained implementation is a low-latency, pipelinable multistage processing element (PE), providing a substantial decrease in resource utilization and increase in computation throughput when compared to state of the art solutions. The implementation solution is also fully scalable and can be efficiently reconfigured according to the DNA sequence sizes and performance requirements of the system architecture. The implementation solution presented in the paper can efficiently scale up to 250MHz obtaining 14746 Alignments/s using a single S-W core with 4 PEs, and up to 31.8 Mega-Alignments/min using 36 S-W cores on the same FPGA for sequences of 160×100 nucleotides.
本文介绍了执行DNA和蛋白质序列比对的史密斯-沃特曼(S-W)算法实现的设计空间探索的结果。通过开发实现该算法的动态数据流程序,并直接对FPGA HDL进行高级合成(HLS),获得了设计探索研究和FPGA实现。所获得的实现的主要特点是低延迟、可管道化的多阶段处理元素(PE),与最先进的解决方案相比,大大降低了资源利用率,提高了计算吞吐量。实现方案也是完全可扩展的,可以根据DNA序列大小和系统架构的性能要求有效地重新配置。本文提出的实现方案可以有效地扩展到250MHz,使用单个带有4个pe的s - w内核获得14746个Alignments/s,在同一FPGA上使用36个s - w内核获得高达31.8个Mega-Alignments/min,用于160×100核苷酸序列。
{"title":"Design space exploration of dataflow-based Smith-Waterman FPGA implementations","authors":"S. Brunet, E. Bezati, M. Mattavelli","doi":"10.1109/SiPS.2017.8109982","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109982","url":null,"abstract":"The paper presents the results of design space explorations for the implementation of the Smith-Waterman (S-W) algorithm performing DNA and protein sequences alignment. Both design explorations studies and FPGA implementations are obtained by developing a dynamic dataflow program implementing the algorithm and by direct high-level synthesis (HLS) to FPGA HDL. The main feature of the obtained implementation is a low-latency, pipelinable multistage processing element (PE), providing a substantial decrease in resource utilization and increase in computation throughput when compared to state of the art solutions. The implementation solution is also fully scalable and can be efficiently reconfigured according to the DNA sequence sizes and performance requirements of the system architecture. The implementation solution presented in the paper can efficiently scale up to 250MHz obtaining 14746 Alignments/s using a single S-W core with 4 PEs, and up to 31.8 Mega-Alignments/min using 36 S-W cores on the same FPGA for sequences of 160×100 nucleotides.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127051205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analysing the performance of divide-and-conquer sequential matrix diagonalisation for large broadband sensor arrays 大型宽带传感器阵列分治顺序矩阵对角化性能分析
Pub Date : 2017-10-03 DOI: 10.1109/SiPS.2017.8109976
Fraser K. Coutts, K. Thompson, Stephan Weiss, I. Proudler
A number of algorithms capable of iteratively calculating a polynomial matrix eigenvalue decomposition (PEVD) have been introduced. The PEVD is an extension of the ordinary EVD to polynomial matrices and will diagonalise a parahermitian matrix using paraunitary operations. Inspired by recent work towards a low complexity divide-and-conquer PEVD algorithm, this paper analyses the performance of this algorithm — named divide-and-conquer sequential matrix diagonalisation (DC-SMD) — for applications involving broadband sensor arrays of various dimensionalities. We demonstrate that by using the DC-SMD algorithm instead of a traditional alternative, PEVD complexity and execution time can be significantly reduced. This reduction is shown to be especially impactful for broadband multichannel problems involving large arrays.
介绍了一些能够迭代计算多项式矩阵特征值分解(PEVD)的算法。PEVD是将普通EVD扩展到多项式矩阵,并将使用拟合运算对角化拟合矩阵。受最近对低复杂度分治PEVD算法的研究启发,本文分析了该算法的性能-命名为分治顺序矩阵对角化(DC-SMD) -用于涉及各种维度宽带传感器阵列的应用。我们证明,通过使用DC-SMD算法而不是传统的替代算法,可以显着降低PEVD的复杂性和执行时间。这种减少被证明对涉及大型阵列的宽带多通道问题特别有影响。
{"title":"Analysing the performance of divide-and-conquer sequential matrix diagonalisation for large broadband sensor arrays","authors":"Fraser K. Coutts, K. Thompson, Stephan Weiss, I. Proudler","doi":"10.1109/SiPS.2017.8109976","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109976","url":null,"abstract":"A number of algorithms capable of iteratively calculating a polynomial matrix eigenvalue decomposition (PEVD) have been introduced. The PEVD is an extension of the ordinary EVD to polynomial matrices and will diagonalise a parahermitian matrix using paraunitary operations. Inspired by recent work towards a low complexity divide-and-conquer PEVD algorithm, this paper analyses the performance of this algorithm — named divide-and-conquer sequential matrix diagonalisation (DC-SMD) — for applications involving broadband sensor arrays of various dimensionalities. We demonstrate that by using the DC-SMD algorithm instead of a traditional alternative, PEVD complexity and execution time can be significantly reduced. This reduction is shown to be especially impactful for broadband multichannel problems involving large arrays.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"125 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114010169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Direction-of-arrival estimation of coherent narrowband signals with arbitrary linear array 任意线阵相干窄带信号的到达方向估计
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109984
Xiao Chen, J. Xin, Nanning Zheng, A. Sano
In this paper, we consider the direction-of-arrivals (DOAs) estimation of coherent narrowband signals impinging on an arbitrary linear array in a computational efficient way. A new interpolation transform based modified Capon beam-forming method is proposed without eigendecomposition, where the arbitrary linear array is transformed to a virtual uniform linear array (ULA) by utilizing the interpolation technique, and then the coherency of incident signals can be decorrelated by employing the spatial smoothing preprocessing. Further by increasing the power of array covariance matrix, a modified Capon beamformer is used to estimate the DOAs, where the component corresponding to the signal subspace is suppressed. The effectiveness of the proposed method is verified through numerical examples, and the simulation results show that the proposed method performs as well as the subspace-based method at low signal to noise ratio (SNR) or with small number of snapshots.
在本文中,我们考虑了相干窄带信号在任意线性阵列上的到达方向估计。提出了一种不需要特征分解的基于插值变换的改进Capon波束形成方法,利用插值技术将任意线性阵列变换为虚拟均匀线性阵列,然后通过空间平滑预处理对入射信号进行相干去相关处理。进一步通过增大阵列协方差矩阵的功率,采用改进的Capon波束形成器估计doa,其中抑制信号子空间对应的分量。通过数值算例验证了所提方法的有效性,仿真结果表明,在低信噪比和少量快照情况下,所提方法的性能与基于子空间的方法相当。
{"title":"Direction-of-arrival estimation of coherent narrowband signals with arbitrary linear array","authors":"Xiao Chen, J. Xin, Nanning Zheng, A. Sano","doi":"10.1109/SiPS.2017.8109984","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109984","url":null,"abstract":"In this paper, we consider the direction-of-arrivals (DOAs) estimation of coherent narrowband signals impinging on an arbitrary linear array in a computational efficient way. A new interpolation transform based modified Capon beam-forming method is proposed without eigendecomposition, where the arbitrary linear array is transformed to a virtual uniform linear array (ULA) by utilizing the interpolation technique, and then the coherency of incident signals can be decorrelated by employing the spatial smoothing preprocessing. Further by increasing the power of array covariance matrix, a modified Capon beamformer is used to estimate the DOAs, where the component corresponding to the signal subspace is suppressed. The effectiveness of the proposed method is verified through numerical examples, and the simulation results show that the proposed method performs as well as the subspace-based method at low signal to noise ratio (SNR) or with small number of snapshots.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114901722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient scalable hardware architecture for highly performant encoded neural networks 用于高性能编码神经网络的高效可扩展硬件架构
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109986
Hugues Wouafo, C. Chavet, P. Coussy, R. Danilo
Different neural network models have been proposed to design efficient associative memories like Hopfield networks, Boltzmann machines or Cogent confabulation. Compared to the classical models, Encoded Neural Network (ENN) is a recently introduced formalism with a proven higher efficiency. This model has been improved through different contributions like Clone-based ENN (CbNNs) or Sparse ENNs (S-ENNs) which enhance either the capacity of the original ENN or its retrieving performances. However, only very few works explored its hardware implementation for embedded applications. In this paper, we introduce a clone-based sparse neural network model (SC-ENN), that gathers the enhancements of the existing approaches in a single formal model. In addition, we present a dedicated scalable hardware architecture to implement SC-ENN. This work leads to significant complexity and area reduction without affecting neither memorizing nor retrieving performances. By only handling the most relevant information provided by the model, our proposed approach is far less expensive compared to state of the art solutions.
人们提出了不同的神经网络模型来设计高效的联想记忆,如Hopfield网络、玻尔兹曼机或Cogent虚构。与经典模型相比,编码神经网络(ENN)是最近才被引入的一种形式,具有更高的效率。该模型通过不同的贡献得到改进,如基于克隆的新神经网络(CbNNs)或稀疏新神经网络(S-ENNs),它们增强了原始新神经网络的容量或检索性能。然而,只有很少的作品探讨了嵌入式应用程序的硬件实现。本文介绍了一种基于克隆的稀疏神经网络模型(SC-ENN),该模型将现有方法的改进功能集中在一个形式模型中。此外,我们提出了一个专用的可扩展硬件架构来实现SC-ENN。这项工作在不影响记忆和检索性能的情况下显著降低了复杂性和面积。通过只处理模型提供的最相关的信息,我们提出的方法与最先进的解决方案相比要便宜得多。
{"title":"Efficient scalable hardware architecture for highly performant encoded neural networks","authors":"Hugues Wouafo, C. Chavet, P. Coussy, R. Danilo","doi":"10.1109/SiPS.2017.8109986","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109986","url":null,"abstract":"Different neural network models have been proposed to design efficient associative memories like Hopfield networks, Boltzmann machines or Cogent confabulation. Compared to the classical models, Encoded Neural Network (ENN) is a recently introduced formalism with a proven higher efficiency. This model has been improved through different contributions like Clone-based ENN (CbNNs) or Sparse ENNs (S-ENNs) which enhance either the capacity of the original ENN or its retrieving performances. However, only very few works explored its hardware implementation for embedded applications. In this paper, we introduce a clone-based sparse neural network model (SC-ENN), that gathers the enhancements of the existing approaches in a single formal model. In addition, we present a dedicated scalable hardware architecture to implement SC-ENN. This work leads to significant complexity and area reduction without affecting neither memorizing nor retrieving performances. By only handling the most relevant information provided by the model, our proposed approach is far less expensive compared to state of the art solutions.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A robust data-driven approach to the decoding of pyloric neuron activity 一个强大的数据驱动的方法解码幽门神经元的活动
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110017
Filipa dos Santos, Péter András, D. Collins, K. Lam
The combination of intra and extra-cellular recording of small neuronal circuits such as stomatogastric nervous systems of the crab (Cancer borealis) is well documented and routinely practised. Voltage sensitive dye imaging (VSDi) is a promising technology for the simultaneous monitoring of neuronal activities in such a system. However, integrating data obtained from optical VSDi and electrophysiological recording of the lateral ventricular nerve (lvn) is a complex and exacting task. Our early work demonstrated some of the concepts and principle involved. In this paper, we examine and report on the results obtained from the application of signal processing techniques to three datasets for which we had VSDi and lvn data. Whilst significant challenges remain, we show that such an approach offers the possibility of real-time monitoring using automated analysis of VSDi data streams without the requirement for either extracellular (lvn) or intracellular recording.
结合小神经元回路的细胞内和细胞外记录,如螃蟹的口胃神经系统(Cancer borealis),有很好的记录和常规实践。电压敏感染料成像(VSDi)是一种很有前途的技术,可以在这种系统中同时监测神经元的活动。然而,整合从光学VSDi和电生理记录的侧脑神经(lvn)获得的数据是一项复杂而艰巨的任务。我们早期的工作展示了一些相关的概念和原理。在本文中,我们检查并报告了信号处理技术应用于三个数据集的结果,其中我们有VSDi和lvn数据。虽然仍然存在重大挑战,但我们表明,这种方法提供了使用VSDi数据流的自动分析进行实时监测的可能性,而不需要细胞外(lvn)或细胞内记录。
{"title":"A robust data-driven approach to the decoding of pyloric neuron activity","authors":"Filipa dos Santos, Péter András, D. Collins, K. Lam","doi":"10.1109/SiPS.2017.8110017","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8110017","url":null,"abstract":"The combination of intra and extra-cellular recording of small neuronal circuits such as stomatogastric nervous systems of the crab (Cancer borealis) is well documented and routinely practised. Voltage sensitive dye imaging (VSDi) is a promising technology for the simultaneous monitoring of neuronal activities in such a system. However, integrating data obtained from optical VSDi and electrophysiological recording of the lateral ventricular nerve (lvn) is a complex and exacting task. Our early work demonstrated some of the concepts and principle involved. In this paper, we examine and report on the results obtained from the application of signal processing techniques to three datasets for which we had VSDi and lvn data. Whilst significant challenges remain, we show that such an approach offers the possibility of real-time monitoring using automated analysis of VSDi data streams without the requirement for either extracellular (lvn) or intracellular recording.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129662906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Forward-substitution-based generalized eigenvalue decomposition processor for MU-MIMO precoding 基于前向替换的MU-MIMO预编码广义特征值分解处理器
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109994
Chun-An Chen, Chiao-En Chen, Yuan-Hao Huang
To improve the spectrum efficiency in wireless communication systems, multiple-input multiple-output (MIMO) technology uses multiple antennas and allows several users to share the same spectrum and antennas by using precoding technique. In the leakage-based precoding technique, generalized eigenvalue decomposition (GEVD) must generate many precoding matrices for all users in the base station to avoid co-channel interference. This paper presents a GEVD algorithm based on forward substitution (FS) scheme to avoid matrix inversion operations. This research also designed and implemented the GEVD processor by using a 40nm CMOS technology. The synthesis results show that the FS-based GEVD processor can reduce area cost by 52% and improve the processing throughput by 12% compared to our previous GEVD [1] processor based on triangular matrix inversion with block multiplication.
为了提高无线通信系统的频谱效率,多输入多输出(MIMO)技术采用多天线,通过预编码技术允许多个用户共享相同的频谱和天线。在基于泄漏的预编码技术中,广义特征值分解(GEVD)必须为基站内所有用户生成多个预编码矩阵,以避免同信道干扰。提出了一种基于前向替换(FS)的GEVD算法,避免了矩阵的反演操作。本研究还设计并实现了采用40nm CMOS技术的GEVD处理器。综合结果表明,与之前基于块乘法三角矩阵反演的GEVD[1]处理器相比,基于fs的GEVD处理器可以减少52%的面积成本,提高12%的处理吞吐量。
{"title":"Forward-substitution-based generalized eigenvalue decomposition processor for MU-MIMO precoding","authors":"Chun-An Chen, Chiao-En Chen, Yuan-Hao Huang","doi":"10.1109/SiPS.2017.8109994","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109994","url":null,"abstract":"To improve the spectrum efficiency in wireless communication systems, multiple-input multiple-output (MIMO) technology uses multiple antennas and allows several users to share the same spectrum and antennas by using precoding technique. In the leakage-based precoding technique, generalized eigenvalue decomposition (GEVD) must generate many precoding matrices for all users in the base station to avoid co-channel interference. This paper presents a GEVD algorithm based on forward substitution (FS) scheme to avoid matrix inversion operations. This research also designed and implemented the GEVD processor by using a 40nm CMOS technology. The synthesis results show that the FS-based GEVD processor can reduce area cost by 52% and improve the processing throughput by 12% compared to our previous GEVD [1] processor based on triangular matrix inversion with block multiplication.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123853973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs 用于混合基数-2/3/4/5 fft的无乘法器可重构处理元件
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110007
F. Qureshi, Muazam Ali, J. Takala
This paper presents area-efficient building blocks for computing fast Fourier transform (FFT): multiplierless processing elements to be used for computing of radix-3 and radix-5 butterflies and reconfigurable processing element supporting mixed radix-2/3/4/5 FFT algorithms. The proposed processing elements are based on Wingorad Fourier transform algorithm. However, multiplication is performed by constant multiplier instead of a general complex-valued multiplier. The proposed process elements have potential use in both pipelined and memory based FFT architectures, where the non-power-of-two sizes are required. The results show that the proposed multiplierless processing elements reduce the significant hardware cost in terms of adders.
本文提出了计算快速傅里叶变换(FFT)的面积高效构建块:用于计算基数3和基数5蝴蝶的无乘法器处理单元和支持混合基数2/3/4/5 FFT算法的可重构处理单元。所提出的处理元素基于Wingorad傅立叶变换算法。然而,乘法是由常数乘法器而不是一般的复值乘法器来执行的。所建议的过程元素在流水线和基于内存的FFT体系结构中都有潜在的用途,其中需要非2次幂的大小。结果表明,所提出的无乘法器处理元件在加法器方面显著降低了硬件成本。
{"title":"Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs","authors":"F. Qureshi, Muazam Ali, J. Takala","doi":"10.1109/SiPS.2017.8110007","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8110007","url":null,"abstract":"This paper presents area-efficient building blocks for computing fast Fourier transform (FFT): multiplierless processing elements to be used for computing of radix-3 and radix-5 butterflies and reconfigurable processing element supporting mixed radix-2/3/4/5 FFT algorithms. The proposed processing elements are based on Wingorad Fourier transform algorithm. However, multiplication is performed by constant multiplier instead of a general complex-valued multiplier. The proposed process elements have potential use in both pipelined and memory based FFT architectures, where the non-power-of-two sizes are required. The results show that the proposed multiplierless processing elements reduce the significant hardware cost in terms of adders.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130281217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A joint spatial texture analysis/watermarking system for digital image authentication 用于数字图像认证的空间纹理分析/水印联合系统
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109968
Musab Ghadi, L. Laouamer, Laurent Nana, A. Pascu
A watermarking system ensures the reliability of images transmitted over public networks by asserting their authenticity. The texture property of host image is one of the most interesting characteristics that can be exploited to design image authentication systems. The importance of texture property emerged from the principles of Human Visual System (HVS), where modifying the spatial pixels of highly textured regions within host image increases the imperceptibility and the robustness against different image processing attacks. Many efficient features known in the literature are used to define the texture property of host image, but all of them are intangible. The model proposed in this paper suggests to solve this intangibility by applying one of Multi-Criteria Decision Making (MCDM) methods, in order to define highly textured blocks within host image to hold the secret data. The proposed model has been tested on grayscale image and the experiments result shows high level of imperceptibility and robustness against different singular and hybrid attacks.
水印系统通过确认图像的真实性来确保在公共网络上传输的图像的可靠性。主机图像的纹理特性是可以用来设计图像认证系统的最有趣的特性之一。纹理属性的重要性来自于人类视觉系统(HVS)的原理,其中修改宿主图像中高度纹理区域的空间像素增加了对不同图像处理攻击的不可感知性和鲁棒性。文献中已知的许多有效特征被用来定义主图像的纹理属性,但它们都是无形的。本文提出的模型通过多准则决策(Multi-Criteria Decision Making, MCDM)方法中的一种来解决这种无形性,在主图像中定义高度纹理化的块来保存秘密数据。该模型在灰度图像上进行了测试,实验结果表明,该模型对不同的奇异攻击和混合攻击具有较高的不可感知性和鲁棒性。
{"title":"A joint spatial texture analysis/watermarking system for digital image authentication","authors":"Musab Ghadi, L. Laouamer, Laurent Nana, A. Pascu","doi":"10.1109/SiPS.2017.8109968","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109968","url":null,"abstract":"A watermarking system ensures the reliability of images transmitted over public networks by asserting their authenticity. The texture property of host image is one of the most interesting characteristics that can be exploited to design image authentication systems. The importance of texture property emerged from the principles of Human Visual System (HVS), where modifying the spatial pixels of highly textured regions within host image increases the imperceptibility and the robustness against different image processing attacks. Many efficient features known in the literature are used to define the texture property of host image, but all of them are intangible. The model proposed in this paper suggests to solve this intangibility by applying one of Multi-Criteria Decision Making (MCDM) methods, in order to define highly textured blocks within host image to hold the secret data. The proposed model has been tested on grayscale image and the experiments result shows high level of imperceptibility and robustness against different singular and hybrid attacks.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122103295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression 利用显著性驱动逻辑压缩的节能近似华莱士树乘法器
Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109990
Issa Qiqieh, R. Shafik, Ghaith Tarawneh, D. Sokolov, Shidhartha Das, Alexandre Yakovlev
In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental to this approach is configurable lossy logic compression, coupled with low-cost error mitigation. The logic compression is aimed at reducing the number of product rows using progressive bit significance, and thereby decreasing the number of reduction stages in Wallace-tree accumulation. This accounts for substantially lower number of logic counts and lengths of the critical paths at the cost of errors in lower significant bits. These errors are minimised through a parallel error detection logic and compensation vector. To validate the effectiveness of our approach, multiple 8-bit multipliers are designed and synthesized using Synopses Design Compiler with different logic compression levels. Post synthesis experiments showed the trade-offs between energy and accuracy for these compression levels, featuring up to 70% reduction in power-delay product (PDP) and 60% lower area in the case of a multiplier with 4-bit logic compression. These gains are achieved at a low loss of accuracy, estimated at less than 0.0554 of mean relative error. To demonstrate the impact of approximation on a real application, a case study of image convolution filter was extensively investigated, which showed up to 62% (without error compensation) and 45% (with error compensation) energy savings when processing image with a multiplier using 4-bit logic compression.
在本文中,我们提出了一种节能的近似乘法器设计方法。这种方法的基础是可配置的有损逻辑压缩,加上低成本的错误缓解。逻辑压缩的目的是使用渐进式位显著性来减少产品行的数量,从而减少华莱士树积累中的约简阶段的数量。这以较低有效位的错误为代价,大大减少了逻辑计数和关键路径的长度。这些错误是通过一个并行的错误检测逻辑和补偿向量最小化。为了验证我们方法的有效性,使用不同逻辑压缩级别的synoses Design Compiler设计和合成了多个8位乘法器。合成后实验显示了这些压缩级别的能量和精度之间的权衡,在具有4位逻辑压缩的乘法器的情况下,功率延迟积(PDP)降低了70%,面积降低了60%。这些增益是在较低的精度损失下实现的,估计小于平均相对误差的0.0554。为了证明近似对实际应用的影响,对图像卷积滤波器的案例研究进行了广泛的研究,结果表明,当使用4位逻辑压缩的乘法器处理图像时,可节省高达62%(无误差补偿)和45%(有误差补偿)的能量。
{"title":"Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression","authors":"Issa Qiqieh, R. Shafik, Ghaith Tarawneh, D. Sokolov, Shidhartha Das, Alexandre Yakovlev","doi":"10.1109/SiPS.2017.8109990","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109990","url":null,"abstract":"In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental to this approach is configurable lossy logic compression, coupled with low-cost error mitigation. The logic compression is aimed at reducing the number of product rows using progressive bit significance, and thereby decreasing the number of reduction stages in Wallace-tree accumulation. This accounts for substantially lower number of logic counts and lengths of the critical paths at the cost of errors in lower significant bits. These errors are minimised through a parallel error detection logic and compensation vector. To validate the effectiveness of our approach, multiple 8-bit multipliers are designed and synthesized using Synopses Design Compiler with different logic compression levels. Post synthesis experiments showed the trade-offs between energy and accuracy for these compression levels, featuring up to 70% reduction in power-delay product (PDP) and 60% lower area in the case of a multiplier with 4-bit logic compression. These gains are achieved at a low loss of accuracy, estimated at less than 0.0554 of mean relative error. To demonstrate the impact of approximation on a real application, a case study of image convolution filter was extensively investigated, which showed up to 62% (without error compensation) and 45% (with error compensation) energy savings when processing image with a multiplier using 4-bit logic compression.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122328894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
期刊
2017 IEEE International Workshop on Signal Processing Systems (SiPS)
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