Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation

Abstract

Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance ($C_{\mathrm{o}\mathrm{v}}$) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDDjunction, which is the physical origin of the $C_{\mathrm{o}\mathrm{v}}$ bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified.