{"title":"A Programmable Bandgap Voltage Reference CMOS ASIC","authors":"G. Kennedy, K. Rinne","doi":"10.1109/IMTC.2005.1604166","DOIUrl":null,"url":null,"abstract":"The research, design and simulation of a programmable bandgap voltage reference is presented. This reference is novel in that it is programmable via a system on chip bus and it comprises a bandgap voltage reference that is digitally modulated by a first order delta sigma modulator and then smoothed by a passive RC filter. The key design objectives are to provide a programmable output from 0 V to 2.5 V approx. with 10-bit resolution and a temperature coefficient of less than 100 ppm/degC over a temperature range from -55degC to +125degC. Another key design objective is to integrate all passive and active components used into one 0.35 micron full custom mixed signal CMOS ASIC","PeriodicalId":244878,"journal":{"name":"2005 IEEE Instrumentationand Measurement Technology Conference Proceedings","volume":"127 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Instrumentationand Measurement Technology Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.2005.1604166","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The research, design and simulation of a programmable bandgap voltage reference is presented. This reference is novel in that it is programmable via a system on chip bus and it comprises a bandgap voltage reference that is digitally modulated by a first order delta sigma modulator and then smoothed by a passive RC filter. The key design objectives are to provide a programmable output from 0 V to 2.5 V approx. with 10-bit resolution and a temperature coefficient of less than 100 ppm/degC over a temperature range from -55degC to +125degC. Another key design objective is to integrate all passive and active components used into one 0.35 micron full custom mixed signal CMOS ASIC
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