Roberta Palau, J. Goebel, Eduardo Zummach, Ramiro Viana, M. Corrêa, G. Corrêa, M. Porto, L. Agostini
{"title":"An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder","authors":"Roberta Palau, J. Goebel, Eduardo Zummach, Ramiro Viana, M. Corrêa, G. Corrêa, M. Porto, L. Agostini","doi":"10.1109/SBCCI55532.2022.9893236","DOIUrl":null,"url":null,"abstract":"This paper presents the first dedicated hardware design in the literature for the Dual Self-Guided Filter (DSGF) from the AOM Video 1 (AV1) video format. The DSGF is one of the last filters in the encoding loop and is used to attenuate blurring artifacts and to improve the subjective video quality. The presented hardware design targets the AV1 decoder and it is able to process Ultra-High Definition (UHD) videos with $3840\\times 2160$ pixels per frame at 60 frames per second when running at 212.86 MHz. The architecture was synthesized to standard cells using the 40 nm TSMC library, using 177.58 kgates and with a power dissipation of 120.21mW.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI55532.2022.9893236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents the first dedicated hardware design in the literature for the Dual Self-Guided Filter (DSGF) from the AOM Video 1 (AV1) video format. The DSGF is one of the last filters in the encoding loop and is used to attenuate blurring artifacts and to improve the subjective video quality. The presented hardware design targets the AV1 decoder and it is able to process Ultra-High Definition (UHD) videos with $3840\times 2160$ pixels per frame at 60 frames per second when running at 212.86 MHz. The architecture was synthesized to standard cells using the 40 nm TSMC library, using 177.58 kgates and with a power dissipation of 120.21mW.