A CMOS CCD video delay line

Abstract

in Figure 2. The delay time difference between two CCD registers (684.5b and 2b) produces a 6 3 . 5 ~ delay time. The IC, using the 684.5b/Zb CCD registers independently can serve as two switchable delay lines, or as two registers together to form a comb filter. The amplitude required for the input clock signal is only lOOmV p-p. Up to 1 V p-p video signals can pass through the delay line without appreciable distortion. The output circuit (Figure 3) contains a double-stage source follower, followed by double stage of a sample and hold circuit and a CMOS inverter amplifier. I n the CMOS circuit the inverter amplifiers have two configurations and are applied in the output circuit. Consequently, a level shift circuit is not necessary between the two inverters. The CMOS inverter amplifier has a wide dynamic range. A comparison of the CMOS inverter amplifier and a conventional N-channel amplifier, together with their total harmonic distortion, is shown in Figure 4. The gain of the amplifier is determined by the transconductance ratio of N-channel and P-channel MOS FETs. Compared to single N-channel inverters, CMOS inverters are free from back gate bias effects. Thus, it is possible to construct high-gain and high-speed amplifiers with CMOS inverters. Characteristic degradations, due to the sample and hold pulse timing, are suppressed by using two-stage sample and hold circuits. The sampling pulse amplitudes are 9V p-p in the first stage and 5V p-p in the second stage insuring a good output signal dynamic range, and a reduction of the sampling pulse coupling.