A high speed counter for analog-to-digital converters

Abstract

A high speed and power efficient synchronous counter is proposed using True Single-Phase Clock (TSPC) based Toggle Flip-Flop (TFF) with the Extended True Single-Phase Clock (E-TSPC) based combinational logic embedded in it. The principle of realizing both synchronous up and down counter at both positive and negative edges using these flip-flops are discussed. Also gray counter is accomplished using same principle. It has been designed in 0.18 μm CMOS process under 1.8 V power supply. The simulation results show that an eight bit synchronous counter can operate at clock frequencies upto 4.54 GHz with the power dissipation of 0.67 mW, while an eight-bit asynchronous counter can operate at clock frequencies upto 5 GHz with the power dissipation of 0.5 mW.