An 8bit 100MHz SAR ADC with 1.5bit Redundancy Method used in Pipelined Structure

Abstract

A 1.5 bit redundancy method is adopted to increase the conversion speed and decrease the power consumption of the DAC switching process. To further speed up the comparison cycle and reduce the variable parasitic capacitance that affect the linearity of the ADC, a monotonic switching down scheme combined with a PMOS-input-low-dynamic-offset (PILDO) comparator was proposed. An 8bit SAR ADC with 1.5 bit redundancy mechanism has been designed in 130nm CMOS SOI process, achieving a ENOB of 7.8 bit.