Asynchronous implementation of modular exponentiation for RSA cryptography

Abstract

This paper presents an efficient VLSI implementation of the modular exponentiation, commonly used in RSA cryptography, based on the asynchronous behavior of the modular multiplication. The basic idea is to partition the operand (multiplier) into several equal-sized segments and then to perform the multiplication and residue calculation of each segment in a micropipelining fashion. Experimental results show that on the average, more than 20% operations can be saved by taking into account the asynchronous behavior of the modular multiplication. The resulting implementation has the characteristics of modular design, simple control, expandable structure, and the critical path is independent of the size of the modulus.