{"title":"A low-power high-speed 1-Mb CMOS SRAM","authors":"Tan Soon-Hwei, Loh Poh-Yee, M. Sulaiman","doi":"10.1109/DELTA.2006.6","DOIUrl":null,"url":null,"abstract":"An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of process, voltage & temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25/spl mu/m 1P5M salicide process and occupies a silicon area of approximately 115mm/sup 2/ (11.5mm /spl times/ 10mm).","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2006.6","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of process, voltage & temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25/spl mu/m 1P5M salicide process and occupies a silicon area of approximately 115mm/sup 2/ (11.5mm /spl times/ 10mm).
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