{"title":"The input pattern fault model and its application","authors":"R. D. Blanton, J. Hayes","doi":"10.1109/EDTC.1997.582441","DOIUrl":null,"url":null,"abstract":"The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit primitive, independent of the design level. Here, we formalize the model and provide a method for analyzing IP faults using single stuck-line (SSL) based tools.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings European Design and Test Conference. ED & TC 97","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1997.582441","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit primitive, independent of the design level. Here, we formalize the model and provide a method for analyzing IP faults using single stuck-line (SSL) based tools.
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