Microbumping technology for hybrid IR detectors, 10μm pitch and beyond

B. Majeed, P. Soussan, P. Le Boterf, P. Bouillon
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引用次数: 2

Abstract

In order to assess the feasibility of a more mass-manufacturable process, IMEC has developed microbump technologies down to 10μm pitch. The micro bumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures. Different test materials with 15, 10 and even 5μm pitch Sn microbumps were processed for a total amount of 640 × 512 (VGA), 1024 × 768 (XGA) and 3072 × 3072 pixels respectively. The microbumped Si chips were assembled with glass chips, InGaAs and HgCdTe compounds and subjected to thermocycling reliability evaluation.
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用于混合红外探测器的微碰撞技术,10μm间距及以上
为了评估更大规模生产工艺的可行性,IMEC开发了小至10μm间距的微凸点技术。微凸点是基于Cu/Ni/Sn半添加剂电镀,并使用与标准封装基础设施完全兼容的工艺在晶圆级构建的。不同的测试材料分别处理了15、10甚至5μm间距的Sn微凸点,总像素分别为640 × 512 (VGA)、1024 × 768 (XGA)和3072 × 3072像素。将微碰撞硅芯片与玻璃芯片、InGaAs和HgCdTe化合物组装,并进行热循环可靠性评估。
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