A switched interconnection infrastructure to tightly-couple a RISC processor core with a coarse grain reconfigurable array

Abstract

This paper describes a novel interconnection infrastructure for a general-purpose system composed of a RISC processor core and a coarse grain run-time reconfigurable array. The proposed infrastructure is based on a non-blocking network of switches and provides a point-to-point connection between the two processing blocks and all the system peripherals. Modifications to the switches and adoption of separated clock domains allowed the achievement of a 3x speed-up in comparison with a bus based interconnection.