A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration

Abstract

This paper proposes a reconfigurable high performance multiplier (RHPM) based on multi-granularity design and parallel acceleration. Capable of supporting multiple precisions for different processing requirements, the RHPM can perform one 32×32, two 16×16, or four 8×8 bit unsigned/signed multiplication, or one 16×16, or two 8×8 bit complex number multiplication. The structures of the partial product generator and the partial product accumulator are improved in the paper, so as to reuse most of the hardware resources. Compression can be completed automatically by means of recording the validity of every bit in the partial product array which accelerates the computation dramatically. The RHPM is implemented with TSMC 28nm technology, exhibiting a 0.68s of the critical path delay, while consuming only 0.6281mW in power. Results show its significant superiority in terms of performance and power efficiency compared with our previous work or other similar products.