G. Edirisooriya, S. Edirisooriya, John P. Robinson
{"title":"A new built-in self-test method based on prestored testing","authors":"G. Edirisooriya, S. Edirisooriya, John P. Robinson","doi":"10.1109/VTEST.1993.313315","DOIUrl":null,"url":null,"abstract":"Built-in-self-test (BIST) schemes provide on-chip circuitry to generate test vectors and to analyze output responses so that testing can be performed without using expensive external testers. The authors present a unified approach to test pattern generation and output compaction. ISCAS benchmark circuits are used to show the applicability of the proposed method.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"168 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313315","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Built-in-self-test (BIST) schemes provide on-chip circuitry to generate test vectors and to analyze output responses so that testing can be performed without using expensive external testers. The authors present a unified approach to test pattern generation and output compaction. ISCAS benchmark circuits are used to show the applicability of the proposed method.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
