A Built-In Self-Test scheme for DDR memory output timing test and measurement

Abstract

This paper presents a Built-In Self-Test (BIST) scheme to measure high speed double data rate (DDR) memory output timing using low cost testers. This technique uses an on-chip pattern generator to generate a time delay between data and data-strobe or clock. The time delay is controlled precisely using a phase interpolator based cycle-by-cycle control method. A novel method for testing the resolution of phase interpolator, which does not need any extra hardware, is also presented. Using the test resolution, a timing pass/fail flag is set and the timing margin is quantified as a multiple of the test clock cycle. Since these test results have high observability, output per-pin timing performance can be diagnosed easily, which is especially good for testing parallel memory interfaces. Moreover, these features make our scheme compatible with low-cost testers and decreases the time-to-market for the chip. The BIST circuit has been implemented using the 0.18-μm CMOS process, and chip measurement results are presented. We obtained a test resolution of 10 ps for testing output timing. Using the fabricated test chip, this paper shows the effects of switching noise, per-pin skews and slew-rate change on output timing variations.