Challenges for spacer and source/drain cavity patterning in CFET devices

Abstract

In a complementary-FET (CFET), n- and p- type transistors are stacked on top of each other. This stacking approach results in very high aspect ratio vertical features which brings critical challenges for nanosheet (NSH), gate, spacer, and source/drain (S/D) cavity patterning. Silicon nitride spacers are commonly used to electrically isolate and protect the silicon gate during S/D epitaxial growth and to precisely define the channel length (Lg) [1-4]. In this work, we will discuss the spacer film opening, the optimization of the S/D cavity profile and propose options to reduce the gate hard mask consumption. We were able to straighten the S/D cavity profile in the SiGe superlattice substrate by tuning specific process parameters, during the various etch and over-etch steps of the stack. Chemical analysis of the sidewall of the cavity, by TEM/EDS, confirmed that the formation of a passivation oxi-nitride compound is key to achieve vertical cavity profile. The chemical mapping of the cavity was done through the Si and SiGe25% sheets. A Si, O and N containing passivation layer is present in the cavity which seems to be thicker at the top and thinner at the bottom of the cavity. Furthermore, polymer capping methods were investigated to reduce the consumption of oxide hard mask (HM) during spacer etch. Process optimization for the cavity shape in the S/D recess etch was conducted using TEM characterization.