1.68μJ/signature-generation 256-bit ECDSA over GF(p) signature generator for IoT devices

Abstract

We have designed and fabricated a 256-bit elliptic curve digital signature algorithm (ECDSA) on a GF(p) signature generation processor in SOTB 65-nm CMOS. We have optimized the pipeline architecture of the Montgomery multiplier by exploiting parallelism, and have achieved 1/50 energy consumption for signature generation, as compared with the previously reported state-of-the-art. Our processor showed correct operation under a wide range of power supply voltages (Vdd) from 1.1 V to 0.25 V, realized a signature generation time (Tsg) of 325 μs at Vdd of 1.1 V and a body bias of VBP = 0.55 V and VBN = 0.55 V, Tsg of 2.3 ms and an energy consumption of 1.68 μJ at Vdd of 0.3 V and a body bias of VBP = 0.3 V and VBN = 0 V, and Tsg of 11 ms and a power consumption of 0.15 mW at Vdd of 0.25 V and a body bias of VBP = 0.37 V and VBN = −0.12 V. Our design demonstrated the lowest power/energy value ever reported and the fastest signature generation ever reported in real silicon.