M. Dinari, G. Mouginot, E. Byk, V. Brunel, C. Chang, L. Brunel, M. Camiade
{"title":"Three Stage 5-18.5 GHz High Gain and High Power Amplifier Based on 0.15 μm GaN Technology","authors":"M. Dinari, G. Mouginot, E. Byk, V. Brunel, C. Chang, L. Brunel, M. Camiade","doi":"10.23919/EUMIC.2018.8539866","DOIUrl":null,"url":null,"abstract":"This paper presents a wideband three stage monolithic HPA design and characterizations. It is realized on UMS 0.15 μm GaN technology on SiC substrate. The main challenge was to find a good trade-off between RF characteristics (power, Power Added Efficiency, gain flatness and Input/Output return loss in a wide frequency range), thermal characteristics, and chip size: this was achieved by combining distributed (first stage) and reactively matched (second and third stages) architectures. The characterization results show an output power from 5.5 W to 9 W, an average PAE of 22% and a small signal gain higher than 30 dB over the frequency band 5-18.5 GHz. These performances are obtained in test fixture, and in Continuous Wave mode (CW).","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EUMIC.2018.8539866","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a wideband three stage monolithic HPA design and characterizations. It is realized on UMS 0.15 μm GaN technology on SiC substrate. The main challenge was to find a good trade-off between RF characteristics (power, Power Added Efficiency, gain flatness and Input/Output return loss in a wide frequency range), thermal characteristics, and chip size: this was achieved by combining distributed (first stage) and reactively matched (second and third stages) architectures. The characterization results show an output power from 5.5 W to 9 W, an average PAE of 22% and a small signal gain higher than 30 dB over the frequency band 5-18.5 GHz. These performances are obtained in test fixture, and in Continuous Wave mode (CW).