Mapping methodology and analysis of matrix-based nanocomputer architectures

Abstract

In this article, a new methodology for mapping applications onto matrix-based nanocomputer architectures is proposed. It takes into account the structural characteristics and connectivity restrictions of cell matrices and can be used (i) for the partitioning and mapping of applications, (ii) for the generation of alternative mapping configurations with required area, power and delay characteristics and (iii) for the comparison of different architectures and adjusting their parameters. The methodology shows significant improvement in routing area (∼36%) and wire width (∼33%) over existing mapping algorithms.