Pub Date : 2011-08-12DOI: 10.1109/NEWCAS.2011.5981232
G. Simard, M. Sawan, D. Massicotte
Neural recording or neural stimulating biomedical implants require a low-power high-speed communication link. We propose a novel modulation scheme for biomedical implants based on Spatial Pulse Position Modulation (SPPM). The principle of this new modulation scheme is presented, a system is developed up to post-layout simulation and is shown to perform up to 200 Mbps using only 750 μW at the transmitter side (3.75 pJ/bit) and 253 μW at the receiver side. The possibility of naturally combining a Viterbi encoder to the system is evoked, and important circuits stemming from the SPPM concept are briefly presented, such as a new receiver topology, based on a resistive bridge and two comparators.
{"title":"Low-power high-speed capacitive transdermal Spatial Pulse Position Modulation communication","authors":"G. Simard, M. Sawan, D. Massicotte","doi":"10.1109/NEWCAS.2011.5981232","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981232","url":null,"abstract":"Neural recording or neural stimulating biomedical implants require a low-power high-speed communication link. We propose a novel modulation scheme for biomedical implants based on Spatial Pulse Position Modulation (SPPM). The principle of this new modulation scheme is presented, a system is developed up to post-layout simulation and is shown to perform up to 200 Mbps using only 750 μW at the transmitter side (3.75 pJ/bit) and 253 μW at the receiver side. The possibility of naturally combining a Viterbi encoder to the system is evoked, and important circuits stemming from the SPPM concept are briefly presented, such as a new receiver topology, based on a resistive bridge and two comparators.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131147196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981265
A. Samir, L. Girardeau, Y. Bert, E. Kussener, W. Rahajandraibe, Herve Barthelemy
A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.
{"title":"771mV, 173nA, 90nm CMOS resistorless trimmable voltage reference","authors":"A. Samir, L. Girardeau, Y. Bert, E. Kussener, W. Rahajandraibe, Herve Barthelemy","doi":"10.1109/NEWCAS.2011.5981265","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981265","url":null,"abstract":"A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981203
Elham Khamsehashari, Y. Audet
A current-mode column readout circuit architecture is presented. The readout circuit is composed of a first-generation current conveyor, a current memory employed as a delta reset sampling unit, a differential amplifier as an integrator and a dynamic comparator. The current-mode active pixel sensor uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a linear-logarithmic response. The pixel response operation is determined in the column readout circuit and a signal is sent to the digital processing unit as an indicator. Experimental results, obtained from test structure, are presented. The circuit was fabricated in a CMOS 0.35um process from Austria Microsystems.
{"title":"Mode detection of a linear-logarithmic current-mode image sensor","authors":"Elham Khamsehashari, Y. Audet","doi":"10.1109/NEWCAS.2011.5981203","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981203","url":null,"abstract":"A current-mode column readout circuit architecture is presented. The readout circuit is composed of a first-generation current conveyor, a current memory employed as a delta reset sampling unit, a differential amplifier as an integrator and a dynamic comparator. The current-mode active pixel sensor uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a linear-logarithmic response. The pixel response operation is determined in the column readout circuit and a signal is sent to the digital processing unit as an indicator. Experimental results, obtained from test structure, are presented. The circuit was fabricated in a CMOS 0.35um process from Austria Microsystems.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125595216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981293
Emily G. Allstot, Andrew Y. Chen, Anna M. R. Dixon, Daibashish Gangopadhyay, Heather Mitsuda, D. Allstot
Compressed sensing (CS) is an emerging signal processing technique that enables sub-Nyquist sampling of sparse signals such as electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) bio-signals. Future CS signal processing systems will exploit significant time- and/or frequency-domain sparsity to achieve ultra-low-power bio-signal acquisition in the analog, digital, or mixed-signal domains. A measurement matrix of random values is key to one form of CS computation. It has been shown for ECG and EMG signals that signal-to-quantization noise ratios (SQNR) > 60 dB with compression factors up to 16X are achievable using uniform or Gaussian 6-bit random coefficients. In this paper, 1-bit random coefficients are shown also to give compression factors up to 16X with similar SQNR performance. This approach reduces hardware and saves energy concomitant with 1-bit versus 6-bit signal processing.
{"title":"Compressed sensing of ECG bio-signals using one-bit measurement matrices","authors":"Emily G. Allstot, Andrew Y. Chen, Anna M. R. Dixon, Daibashish Gangopadhyay, Heather Mitsuda, D. Allstot","doi":"10.1109/NEWCAS.2011.5981293","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981293","url":null,"abstract":"Compressed sensing (CS) is an emerging signal processing technique that enables sub-Nyquist sampling of sparse signals such as electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) bio-signals. Future CS signal processing systems will exploit significant time- and/or frequency-domain sparsity to achieve ultra-low-power bio-signal acquisition in the analog, digital, or mixed-signal domains. A measurement matrix of random values is key to one form of CS computation. It has been shown for ECG and EMG signals that signal-to-quantization noise ratios (SQNR) > 60 dB with compression factors up to 16X are achievable using uniform or Gaussian 6-bit random coefficients. In this paper, 1-bit random coefficients are shown also to give compression factors up to 16X with similar SQNR performance. This approach reduces hardware and saves energy concomitant with 1-bit versus 6-bit signal processing.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126854338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981321
Chien-Hung Kuo, Shu-Li Liao
This paper presents an all-digital 4-bit delta-sigma (ΔΣ) modulator for envelope elimination and restoration (EER)-based polar transmitters. A fast feedback approach is devised by combining the digital truncator with path gains to reduce the propagation delay of feedback loops in modulators. The CMOS standard cell-based design could hence be utilized to implement the proposed modulator at a sampling frequency of 182 MHz. The noise transfer function of the presented ΔΣ modulator has been optimized to obtain a maximally flat noise band to easily meet the EDGE spectrum mask. Experiment results show the presented ΔΣ modulator has the noise power beneath −60 dB below the full-scale EDGE signal within ±20 MHz of the carrier frequency. The measured adjacent channel power ratios and alternate channel power ratio of the proposed modulator also give a 6 dB margin to the EDGE specification at 400 kHz and 600 kHz offsets.
{"title":"An all-digital ΔΣ envelope modulator for EER-based transmitters based on CMOS standard cell design","authors":"Chien-Hung Kuo, Shu-Li Liao","doi":"10.1109/NEWCAS.2011.5981321","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981321","url":null,"abstract":"This paper presents an all-digital 4-bit delta-sigma (ΔΣ) modulator for envelope elimination and restoration (EER)-based polar transmitters. A fast feedback approach is devised by combining the digital truncator with path gains to reduce the propagation delay of feedback loops in modulators. The CMOS standard cell-based design could hence be utilized to implement the proposed modulator at a sampling frequency of 182 MHz. The noise transfer function of the presented ΔΣ modulator has been optimized to obtain a maximally flat noise band to easily meet the EDGE spectrum mask. Experiment results show the presented ΔΣ modulator has the noise power beneath −60 dB below the full-scale EDGE signal within ±20 MHz of the carrier frequency. The measured adjacent channel power ratios and alternate channel power ratio of the proposed modulator also give a 6 dB margin to the EDGE specification at 400 kHz and 600 kHz offsets.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123005512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981271
A. Ajbl, M. Pastre, M. Kayal
This paper presents a voltage-to-current converter as a current-mode output buffering stage for sensor interfaces. The converter can be used in any microsystem needing a current output. It is presented here in the context of a Hall sensor microsystem. The system is fully differential with an output stage that converts a discrete input voltage into a continuous current. The Hall sensor microsystem, using the voltage-to-current back-end, has been fabricated and measured in a 0.35 μm CMOS technology. The entire system performs with non-linearity lower than ±0.08% and maximum output current of ±3mA.
{"title":"A current-mode back-end for a sensor microsystem","authors":"A. Ajbl, M. Pastre, M. Kayal","doi":"10.1109/NEWCAS.2011.5981271","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981271","url":null,"abstract":"This paper presents a voltage-to-current converter as a current-mode output buffering stage for sensor interfaces. The converter can be used in any microsystem needing a current output. It is presented here in the context of a Hall sensor microsystem. The system is fully differential with an output stage that converts a discrete input voltage into a continuous current. The Hall sensor microsystem, using the voltage-to-current back-end, has been fabricated and measured in a 0.35 μm CMOS technology. The entire system performs with non-linearity lower than ±0.08% and maximum output current of ±3mA.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"9 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114032915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981288
Etienne Collard-Fréchette, Georges Kaddoum, G. Gagnon
This paper presents a new coefficient scaling technique to determine the dynamic range of the integrators of sigma delta modulators. This technique relies on numerical optimization of the interstage coefficients to minimize a multi-criteria objective function taking into account the sum of capacitor values implementing the modulator and the voltage swing at each integrator output, for a given target SNR. The optimization process includes the effect of thermal noise at each integrator stage. A user-defined parameter can steer the optimization process priority towards either the size of the capacitors or the integrators output voltage swing, depending on the given application.
{"title":"Dynamic range scaling of sigma-delta modulators based on a multi-criteria optimization process","authors":"Etienne Collard-Fréchette, Georges Kaddoum, G. Gagnon","doi":"10.1109/NEWCAS.2011.5981288","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981288","url":null,"abstract":"This paper presents a new coefficient scaling technique to determine the dynamic range of the integrators of sigma delta modulators. This technique relies on numerical optimization of the interstage coefficients to minimize a multi-criteria objective function taking into account the sum of capacitor values implementing the modulator and the voltage swing at each integrator output, for a given target SNR. The optimization process includes the effect of thermal noise at each integrator stage. A user-defined parameter can steer the optimization process priority towards either the size of the capacitors or the integrators output voltage swing, depending on the given application.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981219
P. Bénabès, Catalin-Adrian Tugui
Novel CMOS technologies are rapidly migrating towards the nanometer world. The design and optimization of complex analog circuits employing these processes is impracticable when using only transistor-level electronic design automation (EDA) tools. Efficient design methodologies including behavioral modeling are inevitable, but the high-level models should incorporate accurate circuit characteristics and technological limitations. One solution consists in using a refined top-down design process where the macro-models are extracted from the analog block elements (e.g. amplifiers, filters) implemented on specific technologies. These fast-simulating models can be used for the high-level simulation and optimization of the entire system. We propose in this paper a complete design methodology employing the above elements and the corresponding application framework based on the interface between MATLAB and CADENCE software tools. SIMULINK and VHDL-AMS are used for the high-level system modeling. A continuous-time (CT) Sigma-Delta modulator application is presented.
{"title":"A high-level modeling framework for the design and optimization of complex CT functions","authors":"P. Bénabès, Catalin-Adrian Tugui","doi":"10.1109/NEWCAS.2011.5981219","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981219","url":null,"abstract":"Novel CMOS technologies are rapidly migrating towards the nanometer world. The design and optimization of complex analog circuits employing these processes is impracticable when using only transistor-level electronic design automation (EDA) tools. Efficient design methodologies including behavioral modeling are inevitable, but the high-level models should incorporate accurate circuit characteristics and technological limitations. One solution consists in using a refined top-down design process where the macro-models are extracted from the analog block elements (e.g. amplifiers, filters) implemented on specific technologies. These fast-simulating models can be used for the high-level simulation and optimization of the entire system. We propose in this paper a complete design methodology employing the above elements and the corresponding application framework based on the interface between MATLAB and CADENCE software tools. SIMULINK and VHDL-AMS are used for the high-level system modeling. A continuous-time (CT) Sigma-Delta modulator application is presented.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122230883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981281
H. Gassara, P. Desgreys, P. Loumeau
Basing on a bandpass ΔΣ modulator model in superconducting technology, we propose to design and implement a time-interleaved parallel architecture for this type of ADC. The interest of such architecture consists in combining oversampling and time-interleaved techniques in order to obtain a high speed and large band superconducting ΔΣ ADC.
{"title":"Parallel architecture for bandpass ΔΣ ADC in superconducting technology","authors":"H. Gassara, P. Desgreys, P. Loumeau","doi":"10.1109/NEWCAS.2011.5981281","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981281","url":null,"abstract":"Basing on a bandpass ΔΣ modulator model in superconducting technology, we propose to design and implement a time-interleaved parallel architecture for this type of ADC. The interest of such architecture consists in combining oversampling and time-interleaved techniques in order to obtain a high speed and large band superconducting ΔΣ ADC.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981240
S. Al-Araji, K. Mezher
An adaptive dual loop phase locked loop (PLL) system with auto selection technique for fast acquisition, reliable locking and improved noise performance is proposed. The system utilizes the wide locking range properties and fast acquisition of the first order loop and enhanced noise performance of the second order loop. The simulation results confirmed the new system's ability to switch between 2nd and 1st order loops in order to acquire fast acquisition, while keeping the loop in lock. In this work, the system is designed to overcome the conflicting requirement of fast acquisition and improved noise performance. This technique is particularly desirable for communication and control applications.
{"title":"Adaptive dual loop phase lock loop with improved performance","authors":"S. Al-Araji, K. Mezher","doi":"10.1109/NEWCAS.2011.5981240","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981240","url":null,"abstract":"An adaptive dual loop phase locked loop (PLL) system with auto selection technique for fast acquisition, reliable locking and improved noise performance is proposed. The system utilizes the wide locking range properties and fast acquisition of the first order loop and enhanced noise performance of the second order loop. The simulation results confirmed the new system's ability to switch between 2nd and 1st order loops in order to acquire fast acquisition, while keeping the loop in lock. In this work, the system is designed to overcome the conflicting requirement of fast acquisition and improved noise performance. This technique is particularly desirable for communication and control applications.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123919988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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