SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI

Abstract

This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port SRAM row decoder show 16% and 57% propagation delay reduction at 1V and 0.5V, respectively. The gain obtained at RVT design standby power is enabled by the wide range N-Well back biasing.