Method for Fast Evaluation of the Circuit Performance After Structural Resynthesis for RSoC

Abstract

The use of reconfigurable system-on-chip logic element re-synthesis in the integrated circuit design flow requires a complete element basis to perform static timing analysis. If the library element is based on a LUT, then characterizing the full library can take a significant amount of time.This paper presents a method for fast evaluation of the circuit performance after structural re-synthesis, which does not require the characterization of the complete library. It consists of initial characterization of the LUT element and dynamic generation of the library, which includes only the temporal parameters of the cells that were obtained as a result of logical synthesis. The method makes it possible to take into account all structural changes in a logic element and perform a static timing analysis without a critical loss of accuracy. The delay of the elements in the generated libraries differs from the characterized libraries by a maximum of 5% and the output transition time by 0.013%.