Degrading fault model for WSI interconnection lines

Abstract

A new fault model is proposed which accounts for both degrading and catastrophic fault types, which exist in WSI/VLSI designs. Fault degrading is the result of a defect mechanism which has no effect on the logical behavior of the circuit, but rather causes performance degradation to the circuit. This degradation is manifested in poor signal propagation delays, and weak noise immunity. However, there are no testing techniques and no fault models that are capable of handling the testing of the degrading fault by using digital fault simulation. A defect model that is capable of mapping degrading defects syndrome into a Boolean behavior (syndrome) would make it possible to use higher speed digital fault simulation techniques, rather than analog parametric testing. This approach for testing is more reliable and would cover both degrading and fatal (catastrophic) faults in the system.<>