Design and technology for DMOS E/D logic

Abstract

The authors discuss two problems which arise in the practical implementation of DMOS to enhancement-depletion (E/D) logic. The first problem relates the optimum design of DMOS logic gates, for which some particular features of the devices must be taken into account. First, the fact that typical short-channel characteristics are obtained from a full-size device deeply modifies the relation existing between electrical characteristics of a gate and its real estate. Second, some deviations from the simplified theory, such as carrier velocity saturation occurring mainly in the driver transistor, must be taken into account when computing the inverter characteristics. Starting from simple mathematical expressions, design rules have been developed and compared to conventional E/D logic. Two design regions, corresponding to two different options in the technology, may be distinguished for DMOS logic.