EHSAT Modeling from Algorithm Description for RTL Model Checking

Abstract

This paper presents a new method to translate Verilog HDT into RTL Model combining algorithm description for high level verification. The model could be used in the enhanced version of a state-of-the-art finite-domain satisfiability (SAT) solver EHSAT to check the verified properties. The enhanced version of EHSAT provides an efficient algorithm to solve the SAT problem for higher level abstraction RTL designs using a hybrid branch-and-bound strategy with conflict-driven learning. This modeling program analyses the control flow of Verilog source codes and generates corresponding statements for the enhanced version EHSAT. This method could largely reduce the scale of model checking and simplify the devices used in EHSAT. Experimental results show that this method can reduce verification problem sizes considerably while comparing with lower level methods.