ASIC receiver for the Pan European digital cellular telephone (GSM)

Abstract

In digital mobile radio, adaptive Viterbi equalizers are used to overcome radio transmission problems caused by multipath fading. Optimum equalizer performance is required to meet the GSM recommendations. On the other hand, the implementation should be minimal in terms of cost, size, and power consumption. These conflicting requirements are solved best by the use of an ASIC. Since the performance of the ASIC-based system must be guaranteed before fabrication, using CAD tools for VLSI design alone is not sufficient. By using a state-of-the-art system simulation tool the complete GSM physical layer was simulated. After optimization of the equalizer algorithm with the help of system simulation, the VLSI design was carried out using a bit-level correspondence between the high-level description (HDL) and system simulator model. From the HDL description the silicon was automatically synthesized.<>