A High-Performance Second-Generation Sparc Mcm

D. Tuckerman, D. Benson, H. Moore, J. Horner, J. Gibbons
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引用次数: 6

Abstract

ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.
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高性能第二代Sparc Mcm
ROSS科技公司和nCHIP公司成功生产了第二代SPARC处理器多芯片模块(MCM)。该模块基于ROSS的hyperSPARC/sup TM/架构,为SPARC市场的性能设定了新的标准。MCM封装在一个45mm平方的256引线陶瓷四平面包装载体中,与ROSS目前的SPARC MCM CYM6111兼容。然而,新模块的时钟速度超过80 MHz,是CYM6111的两倍多,并且在大多数应用中提供3-5倍的性能。整个模块包含六个CMOS芯片:一个包含整数和浮点alu的CPU,一个缓存控制器/内存管理单元,以及四个缓存RAM芯片。每个芯片都使用3.3伏和5.0伏电源,因此MCM基板包含一个分离的电源平面。这些芯片采用nCHIP的nC1000衬底技术互连,该技术集成了铝互连,SiO/sub 2/介电和集成去耦电容器。ROSS的多芯片设计策略不依赖于大规模集成或复杂的制造工艺;同样,nCHIP nC1000基板工艺基于强大的类似ic的技术。这种组合提供了出色的可制造性,并允许快速生产进入大批量。
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