Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753574
K. Boggs, D. Wilcox, D. A. Payne, L. Allen
High dielectric ceramic thin films incorporated into microelectronic packaging will extend both the performance and functions of advanced microelectronic packaging. The low processing temperatures, excellent composition control and low capital manufacturing costs may make the sol-gel film preparation route a prime manufacturing method. For this technique to be a useful alternative to competing vacuum deposition methods, the interactions between the commonly employed packaging materials set and the Sol gel derived films must be understood. To integrate these films into applications the development of thin film stresses and resulting defects must be understood. In this study, we are examining the processing of sol-gel derived barium titanate thin films for use as integrated decoupling capacitors as our model system. Stress measurements are made by measuring curvature of thin film coated wafers as a function of temperature and time. The films exhibit both plastic and elastic behavior at different processing stages. These films are microscopically examined to observe the formation of microstructure including cracking and pinholes. By tailoring the thermal process to the viscoelastic film behavior high quality films may be produced.
{"title":"Stress Development During High Dielectric Ceramic Thin Films Processing","authors":"K. Boggs, D. Wilcox, D. A. Payne, L. Allen","doi":"10.1109/ICMCM.1994.753574","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753574","url":null,"abstract":"High dielectric ceramic thin films incorporated into microelectronic packaging will extend both the performance and functions of advanced microelectronic packaging. The low processing temperatures, excellent composition control and low capital manufacturing costs may make the sol-gel film preparation route a prime manufacturing method. For this technique to be a useful alternative to competing vacuum deposition methods, the interactions between the commonly employed packaging materials set and the Sol gel derived films must be understood. To integrate these films into applications the development of thin film stresses and resulting defects must be understood. In this study, we are examining the processing of sol-gel derived barium titanate thin films for use as integrated decoupling capacitors as our model system. Stress measurements are made by measuring curvature of thin film coated wafers as a function of temperature and time. The films exhibit both plastic and elastic behavior at different processing stages. These films are microscopically examined to observe the formation of microstructure including cracking and pinholes. By tailoring the thermal process to the viscoelastic film behavior high quality films may be produced.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127363466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753547
T. Tessier, B. Adams
This paper outlines a detailed study of the mechanical punching of a variety of non-glass reinforced thin laminates which was carried out to confirm the feasibility of this through-hole generation process. Mechanical punching equipment capable of punching up to 12 holes per second used for this evaluation is capable of generating through-holes down to 60 /spl mu/m in diameter in 50-100 /spl mu/m thick films of an assortment of copper clad thin laminate materials were demonstrated and the salient process parameters discussed. Processes for the fabrication of MCM-L substrates and higher density PWB's using mechanically punched through-holes were also presented.
{"title":"Mechanical Punching of Through-Holes in Thin Laminates for Higher Density MCM-L Fabrication","authors":"T. Tessier, B. Adams","doi":"10.1109/ICMCM.1994.753547","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753547","url":null,"abstract":"This paper outlines a detailed study of the mechanical punching of a variety of non-glass reinforced thin laminates which was carried out to confirm the feasibility of this through-hole generation process. Mechanical punching equipment capable of punching up to 12 holes per second used for this evaluation is capable of generating through-holes down to 60 /spl mu/m in diameter in 50-100 /spl mu/m thick films of an assortment of copper clad thin laminate materials were demonstrated and the salient process parameters discussed. Processes for the fabrication of MCM-L substrates and higher density PWB's using mechanically punched through-holes were also presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125935958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753570
J. Evans, L. Bosley, C. S. Romanczuk, R.W. Johnson
Cost concerns related to the development and manufacturability of multichip modules have limited the wide spread use of MCMs for high-volume, low-cost applications. This paper discusses the many elements necessary to fully evaluate the financial effects of MCM programs. In particular, this paper evaluates a development program for a multichip module design targeted for a high volume automotive electronics control module. Often the added material costs associated with multichip modules prohibit MCM usage for low cost applications. This paper deals with the overall costs and savings associated with MCM development. While each decision to incorporate MCMs within a product design must be made individually, the analysis detailed below provides considerable insight into the overall systems cost involved with MCMs.
{"title":"MCM-L Technology: A Systems Cost Analysis for a High Volume Automotive Electronics Application","authors":"J. Evans, L. Bosley, C. S. Romanczuk, R.W. Johnson","doi":"10.1109/ICMCM.1994.753570","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753570","url":null,"abstract":"Cost concerns related to the development and manufacturability of multichip modules have limited the wide spread use of MCMs for high-volume, low-cost applications. This paper discusses the many elements necessary to fully evaluate the financial effects of MCM programs. In particular, this paper evaluates a development program for a multichip module design targeted for a high volume automotive electronics control module. Often the added material costs associated with multichip modules prohibit MCM usage for low cost applications. This paper deals with the overall costs and savings associated with MCM development. While each decision to incorporate MCMs within a product design must be made individually, the analysis detailed below provides considerable insight into the overall systems cost involved with MCMs.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753538
T. Shimoto, K. Matsui, K. Utsumi
A new MCM-D technology which enables reliable fabrication of high-performance and low cost MCMs has been developed. The technology is based on Cu/Photosensitive-BCB thin-film multilayer structure. The fabrication process is reduced by using the newly developed Photosensitive-BCB, with a conventional photolythography process. The flexibility on design rules is allowed, because the Cu/BCB structure has the advantages of excellent planarization, and low electrical resistance of signal line. Long-term reliability test was successfully done; thermal cycle(-45/spl deg/C/125/spl deg/), high-temperature aging at 125/spl deg/C, and high-temperature/humidity(85/spl deg/C/85%). A prototype of high-density RISC module fabricated with the developed technology passed all the long-term reliability tests. The excellent electrical performance was also proved through the signal transmission tests with the prototype module.
{"title":"Cu/Photosensitive-BCB Thin-Film Multilayer Technology for High-Performance Multichip Module","authors":"T. Shimoto, K. Matsui, K. Utsumi","doi":"10.1109/ICMCM.1994.753538","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753538","url":null,"abstract":"A new MCM-D technology which enables reliable fabrication of high-performance and low cost MCMs has been developed. The technology is based on Cu/Photosensitive-BCB thin-film multilayer structure. The fabrication process is reduced by using the newly developed Photosensitive-BCB, with a conventional photolythography process. The flexibility on design rules is allowed, because the Cu/BCB structure has the advantages of excellent planarization, and low electrical resistance of signal line. Long-term reliability test was successfully done; thermal cycle(-45/spl deg/C/125/spl deg/), high-temperature aging at 125/spl deg/C, and high-temperature/humidity(85/spl deg/C/85%). A prototype of high-density RISC module fabricated with the developed technology passed all the long-term reliability tests. The excellent electrical performance was also proved through the signal transmission tests with the prototype module.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753569
S. Mok
Multichip modules have been used in large numbers of memory applications for over ten years. This paper outlines the use of MCM-D in a high-performance family of SRAM modules designed to take advantage of a number of recent changes in the MCM infrastructure. The products are designed for high volume, high-performance, relatively cost-sensitive insertions in support of current and next-generation microprocessor-based system families. This paper discusses the design and implementation of MicroModule System's ChipFrame cache SRAMS. Included are a discussion of package alternatives reviewed prior to standardization on 28mm 160-lead PQFP, the test strategies employed by both IC suppliers and the MCM foundry, and a summary of reliability programs used in product development and design verification. The discussion will also include sample system implementations using these MCMs.
{"title":"Volume Implementation of MCM-D Based Cache SRAM Products for Workstation and PC Applications","authors":"S. Mok","doi":"10.1109/ICMCM.1994.753569","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753569","url":null,"abstract":"Multichip modules have been used in large numbers of memory applications for over ten years. This paper outlines the use of MCM-D in a high-performance family of SRAM modules designed to take advantage of a number of recent changes in the MCM infrastructure. The products are designed for high volume, high-performance, relatively cost-sensitive insertions in support of current and next-generation microprocessor-based system families. This paper discusses the design and implementation of MicroModule System's ChipFrame cache SRAMS. Included are a discussion of package alternatives reviewed prior to standardization on 28mm 160-lead PQFP, the test strategies employed by both IC suppliers and the MCM foundry, and a summary of reliability programs used in product development and design verification. The discussion will also include sample system implementations using these MCMs.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753548
G. Gengel
This paper will deal with the issues involved with designing a substrate construction and it's associated manufacturing process for cost competitive applications. The substrate system consists of copper-polyimide high density 'layer-pairs' laminated together with an anisotropic conductive adhesive system. The resulting structure has theoretical routing densities on the order of 800 inches/in/sup 2/ per layer pair. The process of manufacturing is based upon roll-to-roll manufacturing techniques pioneered by flexible circuit manufacturers. The parts are kept in roll form until layer pair lamination, avoiding unnecessary handling and damage. However, the manufacturing process has been significantly revised to allow for successful manufacturing of MCMs.
{"title":"A Process for the Manufacture of Cost Competitive MCM Substrates","authors":"G. Gengel","doi":"10.1109/ICMCM.1994.753548","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753548","url":null,"abstract":"This paper will deal with the issues involved with designing a substrate construction and it's associated manufacturing process for cost competitive applications. The substrate system consists of copper-polyimide high density 'layer-pairs' laminated together with an anisotropic conductive adhesive system. The resulting structure has theoretical routing densities on the order of 800 inches/in/sup 2/ per layer pair. The process of manufacturing is based upon roll-to-roll manufacturing techniques pioneered by flexible circuit manufacturers. The parts are kept in roll form until layer pair lamination, avoiding unnecessary handling and damage. However, the manufacturing process has been significantly revised to allow for successful manufacturing of MCMs.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121866807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753607
S. K. Ladd, J. Mandry
While design kits and autorouters are addressing an increasing paction of multichip module (MCW design challenges, the majority of MCM designs are time consuming, error prone, and therefore expensive. Current techniques for the physical design of multichip modules, even with the most advanced design automation tools, do not focus closely enough on the planning and preparation activities that preceed the actual physical design. Without buying new sojiware, engineers designing MCMs can optimize their current design tools to overcome these present-day problems. They must strictly manage component and manufacturing specijkations, automatically generate library parts from electronic, photographic, or faxed inputs), and automatically configure design software settings on a design-by-design basis.
{"title":"Solving Real World MCM Design Problems","authors":"S. K. Ladd, J. Mandry","doi":"10.1109/ICMCM.1994.753607","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753607","url":null,"abstract":"While design kits and autorouters are addressing an increasing paction of multichip module (MCW design challenges, the majority of MCM designs are time consuming, error prone, and therefore expensive. Current techniques for the physical design of multichip modules, even with the most advanced design automation tools, do not focus closely enough on the planning and preparation activities that preceed the actual physical design. Without buying new sojiware, engineers designing MCMs can optimize their current design tools to overcome these present-day problems. They must strictly manage component and manufacturing specijkations, automatically generate library parts from electronic, photographic, or faxed inputs), and automatically configure design software settings on a design-by-design basis.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753532
D. Frye, M. Skinner, R. Heistand, P. Garrou, T. Tessier
The Envision/spl TM/ cost model has been extended to allow an economic evaluation of Large Area Processing (LAP) techniques to fabricate MCM D and LD substrates. The model is based on the unit operation analysis of the capital, material, utilities and workforce requirements per thin film layer (dielectric and conductor layer pair). Comparisons are readily made between sputtered and plated metallurgy with and without metal barrier layers; and between dry etchable, and photosensitive dielectrics. Sensitivity analysis has been performed on coating tool cost, throughput and efficiency of the coating process and the type of tools and materials used to generate vias. More than a threefold cost differential exists between sow of the manufacturing scenarios, and more than a ten fold cost differential exists between IC MCM based fabrication and LAP MCM fabrication. This model is applicable to LAP MCM-D, MCM-CD and MCM-LD manufacturing.
{"title":"Cost Implications of Large Area MCM Processing","authors":"D. Frye, M. Skinner, R. Heistand, P. Garrou, T. Tessier","doi":"10.1109/ICMCM.1994.753532","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753532","url":null,"abstract":"The Envision/spl TM/ cost model has been extended to allow an economic evaluation of Large Area Processing (LAP) techniques to fabricate MCM D and LD substrates. The model is based on the unit operation analysis of the capital, material, utilities and workforce requirements per thin film layer (dielectric and conductor layer pair). Comparisons are readily made between sputtered and plated metallurgy with and without metal barrier layers; and between dry etchable, and photosensitive dielectrics. Sensitivity analysis has been performed on coating tool cost, throughput and efficiency of the coating process and the type of tools and materials used to generate vias. More than a threefold cost differential exists between sow of the manufacturing scenarios, and more than a ten fold cost differential exists between IC MCM based fabrication and LAP MCM fabrication. This model is applicable to LAP MCM-D, MCM-CD and MCM-LD manufacturing.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126790562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753528
R. Short
In today's computers, high pin count packages are required for the high performance, high density silicon being utilized. A significant challenge exists to provide such designs while maintaining a cost effective, high yielding assembly process. This paper discusses Unisys' experience in the development of fine pitch (100/spl mu/m) aluminum wedge bonding for a 591 Pin Grid Array package. Experience and available equipment dictated the package to be die attached using silver glass and wirebonded using 32/spl mu/m aluminum wire. Die attach was well within existing capabilities but the interconnect of over 550 wires on 100/spl mu/m pitch posed a significant challenge. Considerations were given to maximum wire to wire clearance, layer to layer misregistration, wire lengths, bonding tool angles, and fiducials that would provide maximum automatic alignment accuracy. Three dimensional CAD modeling of the bond head and package was followed with an Assembly Test Vehicle (ATV). The ATV was designed to match worst case geometries, and was used to verify concepts developed during 3D modeling. The product was introduced into production in 1993, and has exceeded predicted assembly yields. Although the fine pitch wire bonding was demonstrated on a single chip package, the technology is transportable to multichip applications.
{"title":"Fine Pitch Wedge Bonding for High Density Packaging","authors":"R. Short","doi":"10.1109/ICMCM.1994.753528","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753528","url":null,"abstract":"In today's computers, high pin count packages are required for the high performance, high density silicon being utilized. A significant challenge exists to provide such designs while maintaining a cost effective, high yielding assembly process. This paper discusses Unisys' experience in the development of fine pitch (100/spl mu/m) aluminum wedge bonding for a 591 Pin Grid Array package. Experience and available equipment dictated the package to be die attached using silver glass and wirebonded using 32/spl mu/m aluminum wire. Die attach was well within existing capabilities but the interconnect of over 550 wires on 100/spl mu/m pitch posed a significant challenge. Considerations were given to maximum wire to wire clearance, layer to layer misregistration, wire lengths, bonding tool angles, and fiducials that would provide maximum automatic alignment accuracy. Three dimensional CAD modeling of the bond head and package was followed with an Assembly Test Vehicle (ATV). The ATV was designed to match worst case geometries, and was used to verify concepts developed during 3D modeling. The product was introduced into production in 1993, and has exceeded predicted assembly yields. Although the fine pitch wire bonding was demonstrated on a single chip package, the technology is transportable to multichip applications.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129293185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753545
M. Martínez, D. Gibson, L. Matthew, T. DiStefano, J. Cofield
One of the technical issues obstructing progress in MCMs is the lack of a cost-effective interconnect which is simultaneously small and testable. None of the standard interconnects - TAB, wirebond or C4 - meet both criteria, and bare die test approaches have significant drawbacks. In this paper, a complete MCM solution will be introduced which consists of a micro-BGA interconnect called the TCC (Tessera Compliant Chip) and a TLS (Tessera Laminated Substrate) substrate. The TCC combines aspects of wirebond, TAB and C4 to give a die-sized, testable package for KGD and MCMs. The TLS is fabricated with a parallel lamination process which allows for blind and buried vias, and high wireability. The /spl mu/BGA is attached to the substrate using conventional SMT assembly. Extensive use of the processes and infrastructure which already exist in the packaging industry make the TCC/MCM a logical extension of current technology and a low-cost alternative for high volume packaging applications. This presentation introduces Tessera's MCM solution, and describes a test-module designed to characterize the high-speed performance of the substrate and TCC. An 8-layer substrate (4S/4P) holding a 600 I/0 processor, two controllers and eight SRAMs is used to evaluate wire-length distribution and electrical performance. Simulations of signal integrity, cross-talk, simultaneous switching noise and interconnect delay will be presented. The performance of the TCC/TLS is compared to copper-polyimide MCM-D.
{"title":"The TCC/MCM: /spl mu/BGA on a laminated substrate","authors":"M. Martínez, D. Gibson, L. Matthew, T. DiStefano, J. Cofield","doi":"10.1109/ICMCM.1994.753545","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753545","url":null,"abstract":"One of the technical issues obstructing progress in MCMs is the lack of a cost-effective interconnect which is simultaneously small and testable. None of the standard interconnects - TAB, wirebond or C4 - meet both criteria, and bare die test approaches have significant drawbacks. In this paper, a complete MCM solution will be introduced which consists of a micro-BGA interconnect called the TCC (Tessera Compliant Chip) and a TLS (Tessera Laminated Substrate) substrate. The TCC combines aspects of wirebond, TAB and C4 to give a die-sized, testable package for KGD and MCMs. The TLS is fabricated with a parallel lamination process which allows for blind and buried vias, and high wireability. The /spl mu/BGA is attached to the substrate using conventional SMT assembly. Extensive use of the processes and infrastructure which already exist in the packaging industry make the TCC/MCM a logical extension of current technology and a low-cost alternative for high volume packaging applications. This presentation introduces Tessera's MCM solution, and describes a test-module designed to characterize the high-speed performance of the substrate and TCC. An 8-layer substrate (4S/4P) holding a 600 I/0 processor, two controllers and eight SRAMs is used to evaluate wire-length distribution and electrical performance. Simulations of signal integrity, cross-talk, simultaneous switching noise and interconnect delay will be presented. The performance of the TCC/TLS is compared to copper-polyimide MCM-D.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121395688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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